Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2006-06-06
2006-06-06
Nguyen, Tuan T. (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S230010, C365S230030, C365S230080
Reexamination Certificate
active
07057968
ABSTRACT:
Logic circuits access a memory block by way of an access circuit. The memory block, which is formed of a mixed configuration of DRAMs and an SRAM, realizes the desired memory space. A data output register is provided at the output side of the SRAM so as to synchronize data output timing from the DRAMs with data output timing from the SRAM.
REFERENCES:
patent: 5703822 (1997-12-01), Ikeda
patent: 6584036 (2003-06-01), Kurjanowicz et al.
Hideo Ohwada et al., “A Single-Chip Band-Segmented-Transmission OFDM Demodulator for Digital Terrestrial Television Broadcasting”, 2001 IEEE International Solid-State Circuits Conference.
Toshiba Semiconductor Company, “Embedded DRAM technology” <http://www.semicon.toshiba.co.jp/prd/asIc/index.html>.
Kuroda Naoki
Nakai Yuji
Luu Pho M.
Matsushita Electric - Industrial Co., Ltd.
McDermott Will & Emery LLP
Nguyen Tuan T.
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