Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2006-08-01
2006-08-01
Ho, Hoai V. (Department: 2827)
Static information storage and retrieval
Addressing
Sync/clocking
C365S230080, C365S236000
Reexamination Certificate
active
07085192
ABSTRACT:
In a semiconductor integrated circuit device, a write command decoder decodes a write command and outputs decode pulses. A command counter circuit counts the decode pulses as the number of commands. A latch circuit latches the write aDDRess in response to a count output from the command counter circuit. A latency counter circuit counts a latency in response to the decode pulses. The semiconductor integrated circuit device further includes a circuit for turning on a column selection control signal when the count value of the latency counter circuit exceeds a predetermined latency value and a circuit for outputting the aDDRess latched by the latch circuit as a column aDDRess in response to the column selection control signal being turned on. The semiconductor integrated circuit device performs a write operation to the column aDDRess in response to the column selection control signal being turned on.
REFERENCES:
patent: 6333892 (2001-12-01), Hamamoto et al.
patent: 6671788 (2003-12-01), Shinozaki
patent: 2000-276877 (2000-10-01), None
patent: 2002-25255 (2002-01-01), None
patent: 2002-133866 (2002-05-01), None
Fujisawa Hiroki
Kubouchi Shuichi
Elpida Memory Inc.
Hitachi , Ltd.
Hitachi Ulsi Systems Co., Ltd.
Ho Hoai V.
McGinn IP Law Group PLLC
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