Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2005-12-20
2005-12-20
Tran, Michael (Department: 2827)
Static information storage and retrieval
Interconnection arrangements
C365S230060
Reexamination Certificate
active
06977834
ABSTRACT:
A semiconductor integrated circuit device includes normal bit cells, structural dummy bit cells and timing dummy bit cells having the same structure as that of the normal bit cells, normal word lines electrically connected to the normal bit cells, a first dummy word line electrically coupled to the structural dummy bit cells, and a second dummy word line electrically coupled to the timing dummy bit cells. The second dummy word line is connected in parallel with the first dummy word line.
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Hayakawa Shigeyuki
Midorikawa Tsuyoshi
Onizawa Tadashi
Tanaka Yutaka
DLA Piper Rudnick Gray Cary US LLP.
Kabush″ei Kaishr Toshiba
Tran Michael
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