Semiconductor integrated circuit device

Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage

Reexamination Certificate

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Reexamination Certificate

active

06847252

ABSTRACT:
A semiconductor integrated circuit device having a mechanism of compensating not only circuit operational speed but also variations in leakage current, which includes: a main circuit constructed with CMOS device, a delay monitor for simulating a critical path of the main circuit constructed by a CMOS and monitoring a delay of the path, a PN Vt balance compensation circuit for detecting a threshold voltage difference between a PMOS transistor and an NMOS transistor, and a well bias generating circuit for receiving outputs of the delay monitor and the PN Vt balance compensation circuit and applying a well bias to the delay monitor and the main circuit so as to compensate the operation speed of the delay monitor to a desired speed and reduce a threshold voltage difference between the PMOS and NMOS transistors.

REFERENCES:
patent: 5874851 (1999-02-01), Shiota
patent: 5883544 (1999-03-01), So et al.
patent: 6232793 (2001-05-01), Arimoto et al.
patent: 6466077 (2002-10-01), Miyazaki et al.
patent: 6518825 (2003-02-01), Miyazaki et al.
patent: 6559708 (2003-05-01), Notani
patent: 20010048319 (2001-12-01), Miyazaki et al.
patent: 2001-156261 (2000-04-01), None

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