Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means
Patent
1986-12-12
1987-12-08
Larkins, William D.
Electricity: electrical systems and devices
Safety and protection of systems and devices
Load shunting by fault responsive means
361 91, 361111, 361100, 361118, 357 13, 357 48, 357 50, 357 2313, 357 46, 330207P, 330298, H02H 900, H01L 2704
Patent
active
047121521
ABSTRACT:
A semiconductor integrated circuit device comprising: at least two NPN transistors whose bases and emitters are connected to the ground and whose collectors are connected to an input terminal; one of said NPN transistors having a lower breakdown starting voltage and a higher breakdown maintaining voltage than those of the other of said NPN transistors; and an input portion which has a breakdown maintaining voltage at a high surge voltage breakdown which occurs caused by an application of a high surge voltage input to said input terminal which is lower than that at a low input voltage breakdown which occurs caused by an application of a low surge voltage or an input voltage which rises up gradually.
REFERENCES:
patent: 4131908 (1978-12-01), Daub et al.
patent: 4405933 (1983-09-01), Avery
patent: 4498227 (1985-04-01), Howell et al.
patent: 4527213 (1985-07-01), Ariizumi
patent: 4656491 (1987-04-01), Igarashi
"Advanced Schottky Family", Application Report Texas Instruments, printed in Japan '84, 11, p. 7.
Featherstone D.
Larkins William D.
Mitsubishi Denki & Kabushiki Kaisha
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