Semiconductor integrated circuit device

Details Semiconductor integrated circuit device Semiconductor integrated circuit device

2002-12-18

2004-12-21

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C327S535000, C327S537000

Reexamination Certificate

active

06833750

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to a semiconductor integrated circuit device and more particularly to a semiconductor integrated circuit device operating at a high speed and consuming a small amount of electric power.
BACKGROUND OF THE INVENTION
The power consumed by a semiconductor integrated circuit device using a CMOS circuit consists of power consumed dynamically due to electric charge and discharge at the times of switching and power consumed statically due to subthreshold leak currents. Because dynamic consumption is proportional to the square of supply voltage VDD, dynamic consumption can be reduced effectively by lowering supply voltage VDD. Accordingly the supply voltage VDD of CMOS semiconductor integrated circuit devices of microprocessors, etc. is showing a tendency to lower. Some microprocessors are provided with a power-management mechanism, which enable the microprocessor to operate in two or more modes. In the standby mode of such a microprocessor, clock signals are not fed to the execution unit and, thereby, the dynamic power consumption of the non-operating execution unit is reduced significantly. On the other hand, the static consumption due to subthreshold leak currents has not been reduced.
The operating speed of a CMOS circuit lowers as the supply voltage VDD lowers. To prevent the operating speed from lowering, the threshold voltage of the MOS transistors has to be reduced as the supply voltage VDD lowers. However, when the threshold voltage is reduced, the subthreshold leak currents become significantly large. Accordingly the static consumption due to subthreshold leak currents has become salient as the supply voltage VDD has lowered. Thus hoped for is a semiconductor integrated circuit device of a microprocessor or the like which can operate at a high speed, consuming a small amount of power.
Proposed to solve the above problem is a method of controlling the threshold voltage of MOS transistors with variable substrate voltage [pp. 280-281, Digest of Technical Papers (February 1999), 1999 International Solid-State Circuits Conference]. In the active mode for the normal high-speed operation, the substrate voltage of the PMOS transistor (p-channel MOS transistor) is set to the supply voltage and that of the NMOS transistor (n-channel MOS transistor) is set to the ground voltage. In the standby mode in which high-speed operation is not required of the CMOS circuit, the substrate voltage of the PMOS transistor is raised over the supply voltage VDD and that of the NMOS transistor is lowered below the ground voltage (this operation is hereinafter referred to as “applying low substrate bias”). By applying low substrate voltage to the substrates of the MOS transistors in the standby mode, the threshold voltage of the MOS transistors constituting the CMOS circuit can be raised and, thereby, the static consumption due to subthreshold leak currents can be reduced.
To achieve a CMOS circuit capable of operating at a high speed and a low power-consumption level, the threshold voltages of the MOS transistors are lowered for high-speed operation in the active mode and raised to reduce the subthreshold leak currents in the standby mode.
On the other hand, a microprocessor is required to operate in a wide range of supply voltage. As indicated by the curve (A) in
FIG. 2
, the operating speed of a CMOS circuit decreases rapidly as the supply voltage lowers. Accordingly it is now difficult to run a CMOS circuit at a high speed under low voltage in the active mode just by setting the substrate voltage to the supply voltage and the ground voltage as described above. In the active mode, therefore, the substrate voltage of the PMOS transistor is lowered below the supply voltage VDD and that of the NMOS transistor is raised over the ground voltage (this operation is hereinafter referred to as “applying high substrate bias”) By applying high substrate bias to the substrates of the MOS transistors, their threshold voltage can be reduced and the operating speed of the CMOS circuit can be raised.
On the other hand, applying high substrate bias to the substrates of the MOS transistors means applying forward bias to the substrates in the direction of p-n junction, which increases the leak currents and may induce a latch-up phenomenon to damage the transistors. In the range of low supply voltage, however, the increase in the leak currents is limited and the latch-up phenomenon can be prevented. Therefore, it is preferable that the substrate bias of the PMOS transistor and that of the NMOS transistor are set to the supply voltage and the ground voltage, respectively, in the range of high supply voltage and high substrate bias is applied to the substrates for high-speed operation in the range of low supply voltage. In the standby mode, low substrate bias is applied to the substrates to hold down the leak currents. Thus a CMOS circuit operating at a high speed, consuming a small amount of power, can be achieved.
This invention achieves the following effects by applying low substrate voltage to the substrates in the standby mode in the range of high supply voltage and applying high substrate voltage to the substrates in the range of low supply voltage.
(1) To widen the voltage range in which a CMOS circuit can operate
(2) To reduce the leak currents of a CMOS circuit in the standby mode in the range of high supply voltage and, thereby, reduce the power consumption of the CMOS circuit
(3) To increase the operating speed of a CMOS circuit in the range of low supply voltage
SUMMARY OF THE INVENTION
This invention provides a semiconductor integrated circuit device comprising a main circuit which includes a PMOS transistor having a source-drain channel between a first operating-potential point and a second operating-potential point and a NMOS transistor having a source-drain channel between the first operating-potential point and the second operating-potential point and connected in series to the PMOS transistor. When the changing signal is in a first state, the first operating potential is fed as substrate potential of the PMOS transistor and the second operating potential is fed as substrate potential of the NMOS transistor. When the changing signal is in a second state, first substrate potential lower than the first operating potential is fed as substrate potential of the PMOS transistor and second substrate potential higher than the second operating potential is fed as substrate potential of the NMOS transistor. With such substrate potential, the main circuit operates at high speed.
Preferably, the state of the changing signal is changed over by the first operating potential or the operating speed of the main circuit.
In addition, an active mode and a standby more are provided, and reverse bias is applied to the substrates of MOS transistors in standby mode to reduce the power consumption further.
Other and further objects, features and advantages of the invention will appear more fully from the following description.


REFERENCES:
patent: 5341034 (1994-08-01), Matthews
patent: 5814899 (1998-09-01), Okumura et al.
patent: 5874851 (1999-02-01), Shiota
patent: 6046627 (2000-04-01), Itoh et al.
patent: 6252452 (2001-06-01), Hatori et al.
patent: 6436777 (2002-08-01), Ota

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