Semiconductor integrated circuit device

Details Semiconductor integrated circuit device Semiconductor integrated circuit device

2002-07-16

2004-10-05

Toatley, Jr., Gregory J. (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

Reexamination Certificate

active

06801417

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device including an electrostatic discharge (ESD) protection circuit. In recent years, the degree of integration of a semiconductor integrated circuit device has been increasing along with the technical advancements in the manufacturing process, i.e., a reduction in size and an increase in density. Along with this, such a device has become more vulnerable to damages caused by an electrostatic discharge (hereinafter referred to as a “surge”). There are increased possibilities that an element such as an input circuit, an output circuit, an input/output circuit or an internal circuit is broken, or the characteristics thereof are deteriorated, by a surge entering through an external connection pad, for example. Therefore, the external connection pad is often provided with a protection circuit for protecting the input circuit, the output circuit, the input/output circuit or the internal circuit from a surge.
FIG. 7
is an electric circuit diagram illustrating a configuration of an output circuit and other elements around the output circuit in a conventional semiconductor integrated circuit device including an electrostatic discharge protection circuit. As illustrated in
FIG. 7
, the semiconductor integrated circuit device includes an external connection pad
101
, an electrostatic discharge protection circuit
102
, an output circuit
103
, an output pre-buffer circuit
104
, and an internal circuit
121
, and is configured so that the output circuit
103
is protected by the electrostatic discharge protection circuit
102
from a surge entering through the external connection pad
101
.
The electrostatic discharge protection circuit
102
is provided between the external connection pad
101
and the output circuit
103
, and includes a PMIS transistor
105
, an NMIS transistor
106
, a first resistor
107
and a second resistor
108
. The PMIS transistor
105
includes a source connected to a power supply line
119
for supplying a power supply voltage VDD, a gate connected to the power supply line
119
via the first resistor
107
, a drain connected to the external connection pad
101
, and a substrate region (n well) connected to the power supply line
119
. Moreover, the NMIS transistor
106
includes a source connected to a ground line
120
for supplying a ground voltage VSS, a gate connected to the ground line
120
via the second resistor
108
, a drain connected to the external connection pad
101
, and a substrate region (p well) connected to the ground line
120
.
The output circuit
103
is provided between the electrostatic discharge protection circuit
102
and the output pre-buffer circuit
104
, and includes a PMIS transistor
111
and an NMIS transistor
112
. The PMIS transistor
111
includes a source connected to the power supply line
119
, a gate connected to an output terminal of a first pre-buffer
115
of the output pre-buffer circuit
104
, a drain connected to the external connection pad
101
, and a substrate region (n well) connected to the power supply line
119
. Moreover, the NMIS transistor
112
includes a source connected to the ground line
120
, a gate connected to an output terminal of a second pre-buffer
117
of the output pre-buffer circuit
104
, a drain connected to the external connection pad
101
, and a substrate region (p well) connected to the ground line
120
.
The output pre-buffer circuit
104
for amplifying an output signal from the internal circuit
121
is provided between the internal circuit
121
and the output circuit
103
, and includes a first pre-buffer circuit
116
that includes the first pre-buffer
115
in the last stage and a second pre-buffer current
118
that includes the second pre-buffer
117
in the last stage. The first pre-buffer
115
includes a power supply voltage terminal connected to the power supply line
119
, a ground terminal connected to the ground line
120
, an output terminal connected to the gate of the PMIS transistor
111
of the output circuit
103
, and an input terminal connected to the internal circuit
121
. Moreover, the second pre-buffer
117
includes a power supply voltage terminal connected to the power supply line
119
, a ground terminal connected to the ground line
120
, an output terminal connected to the gate of the NMIS transistor
112
of the output circuit
103
, and an input terminal connected to the internal circuit
121
. Note that the first pre-buffer circuit
116
and the second pre-buffer current
118
each include a plurality of pre-buffers according to the degree of amplification by which an output signal from the internal circuit
121
is to be amplified. The first and second pre-buffer circuits
116
and
118
are configured so that two high and low output signals or two identical output signals are output from the output terminal of the first pre-buffer
115
in the last stage in the first pre-buffer circuit
116
and from the output terminal of the second pre-buffer
117
in the last stage in the second pre-buffer current
118
.
With the conventional semiconductor integrated circuit device having such a configuration, a surge applied between the power supply line
119
and the external connection pad
101
is absorbed by the breakdown of the PMIS transistor
105
, and a surge applied between the ground line
120
and the external connection pad
101
is absorbed by the breakdown of the NMIS transistor
106
. Thus, it is possible to effectively protect the output circuit
103
from a surge entering from the outside through the external connection pad
101
.
Incidentally, a semiconductor integrated circuit device needs to meet an ESD test standard because it is required to assure the user of a certain surge breakdown withstand voltage. In recent years, a human body model (HBM) ESD test standard such as an MIL standard has become the global standard as an ESD test standard, and a semiconductor integrated circuit device needs to meet the HBM test standard.
FIG. 8A
is a circuit diagram illustrating an evaluation circuit for conducting an ESD test based on the HBM test standard, and
FIG. 8B
is a waveform diagram illustrating HBM discharge waveform specifications of the MIL standard.
As illustrated in
FIG. 8A
, the evaluation circuit includes a charging power supply
150
and a discharging resistor
153
having a resistance of R=1.5 k&OHgr;, which are arranged respectively in two circuits (the left-side circuit and the right-side circuit illustrated in FIG.
8
A), which are arranged in parallel with respect to a charging/discharging capacitor
151
having a capacitance of C=100 pF. A selector switch
152
is connected to one electrode of the charging/discharging capacitor
151
, and the selector switch
152
is used to selectively connect the one electrode of the charging/discharging capacitor
151
either to a high-voltage portion of the variable-voltage charging power supply
150
or to the discharging resistor
153
. Moreover, the other electrode of the charging/discharging capacitor
151
is connected to a low-voltage portion of the charging power supply
150
in the left-side circuit illustrated in
FIG. 8A
, and is connected to the discharging resistor
153
in the right-side circuit illustrated in FIG.
8
A. Then, a subject device
154
is placed in the right-side circuit illustrated in
FIG. 8A
between the other electrode of the charging/discharging capacitor
151
and the discharging resistor
153
so as to conduct an ESD test on the subject device
154
.
In the ESD test using the evaluation circuit, one electrode of the charging/discharging capacitor
151
is first connected to the charging power supply
150
by using the selector switch
152
. Then, the left-side circuit illustrated in
FIG. 8A
becomes a closed circuit, and the charging/discharging capacitor
151
is charged by the charging power supply
150
so that the charged voltage thereof is 4000 V, for example. Then, the electrode of the charging/discharging capacitor
151
is switche

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