Semiconductor integrated circuit device

Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – With pn junction isolation

Reexamination Certificate

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Details

C257S173000, C257S355000, C257S773000, C257S784000

Reexamination Certificate

active

06730985

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a protection circuit of a semiconductor integrated circuit device, specifically to a protection circuit with reduced wiring.
2. Description of the Related Art
A semiconductor integrated circuit device has a possibility of breakdown when an excessive external voltage is applied to its input pin. Various kinds of input protection circuits are incorporated in semiconductor integrated circuit devices to prevent this breakdown.
For example, a poly silicon gate MOS integrated circuit is provided with a protection circuit
80
as shown in FIG.
11
. The protection circuit
80
includes two diodes D
3
and D
4
connected in series. A cathode of the protection diode D
3
is connected to Vcc (power supply voltage), while an anode of the protection diode D
4
is connected to GND (ground voltage or reference voltage). An input terminal
81
is connected to a connecting node
83
between the two protection diodes D
3
and D
4
and further connected to an internal circuit through a terminal
82
.
An excessive external voltage due to an electrostatic discharge, or the like, is applied to the input terminal
81
of the protection circuit
80
. When a voltage higher than Vcc is applied, the protection diode D
3
conducts to clamp the voltage at the connecting node
83
, and keeps the internal circuit beyond the terminal
82
from the high voltage. Similarly, when a negative high voltage lower than GND is applied, the protection diode D
4
conducts to clamp the voltage at the connecting node
83
, and keeps the internal circuit beyond the terminal
82
from the negative high voltage.
FIG. 12
is a plan view of a conventional semiconductor integrated circuit device, that is, an LSI
100
with the protection circuit
80
. The LSI
100
includes three circuit blocks
101
A-
101
C, 16 pads
102
A-
102
P and 16 protection circuits
104
A-
104
P. The circuit block denotes a circuit containing many elements such as resistances, transistors and capacitors.
Each of the pads
102
A-
102
P is connected with each of the circuit blocks
101
A-
101
C through an interconnection
103
. Each of the protection circuits
104
A-
104
P is connected with each of the pads
102
A-
102
P through an interconnection
105
, respectively.
Each of the protection circuits
104
A-
104
P contains the protection circuit
80
shown in FIG.
11
and requires two interconnections (not shown) to electrically connect with a Vcc wiring and a GND wiring formed in the LSI
100
. An area each of the protection circuits
104
A-
104
P takes up is about ⅓ to ½ of that of each of the pads
102
A-
102
P.
In the layout design of the semiconductor integrated circuit device shown in
FIG. 12
, placement of the elements is usually determined through the following procedures.
First, three circuit blocks
101
A-
101
C are disposed around a center of the LSI
100
. Positional relationship among positions of the three circuit blocks is determined considering die size and functionality. In
FIG. 12
, the circuit blocks
101
A and
101
B having the same area are placed parallel to the largest circuit block
101
C.
Second, the pads
102
A-
102
P are disposed at regular intervals around the three circuit blocks
101
A-
101
C.
Third, the protection circuits
104
A-
104
P are disposed in the LSI
100
. Since each of the protection circuits
104
A-
104
P takes up a small area than each of the pads
102
A-
102
P, each of the protection circuits
104
A-
104
P is placed in an empty space, or so-called a dead space, between the circuit blocks
101
A-
101
C and the pads
102
A-
102
P.
Then, interconnections
103
,
105
are disposed. In addition, the Vcc wiring and the GND wiring for the protection circuits
104
A-
104
P are disposed.
However, there are the following disadvantages when the elements of the conventional semiconductor integrated circuit device shown in
FIG. 12
are disposed.
First, there are crossings between the interconnections
103
and the interconnections
105
, since the protection circuits
104
A-
104
P are disposed utilizing the so-called dead space in the LSI
100
. Looking at the pad
102
A and the protection circuit
104
A in the lower right corner of the LSI
100
in
FIG. 12
, for example, the interconnection
103
and the interconnection
105
intersect each other.
The crossing of the interconnection
103
and the interconnection
105
may cause a trouble such as a short circuit an interference in signal lines. In addition, the interconnections
103
and
105
and the Vcc and GND wiring, with which the protection circuits
104
A-
104
P are connected, are intertwined with each other complicatedly. This may cause an unexpected adverse effects in a designed layout, requiring a thicker interlayer isolation film or more via holes.
Second, in the semiconductor integrated circuit device of recent years which has multi layer structure and thus requires complicated manufacturing processes, larger number of interconnections increases the impedance of the interconnections, resulting in deterioration in characteristics of the LSI
100
.
SUMMARY OF THE INVENTION
The invention provides a semiconductor integrated circuit device that includes a circuit block, a pad electrically connected to the circuit block and a protection circuit integrated with the pad as an integrated device element. An internal electrical connection is provided within the integrated device element between the pad and the protection circuit.


REFERENCES:
patent: 4839768 (1989-06-01), Daniele et al.
patent: 5223737 (1993-06-01), Canclini
patent: 5293057 (1994-03-01), Ho et al.
patent: 5473169 (1995-12-01), Ker et al.
patent: 5696404 (1997-12-01), Murari et al.
patent: 6303445 (2001-10-01), Ma
patent: 2001-127249 (2001-11-01), None

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