Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Current driver
Reexamination Certificate
2001-08-17
2004-09-28
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Current driver
C327S566000
Reexamination Certificate
active
06798255
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device and in particular to a semiconductor integrated circuit device having a large chip size and a fine wiring in which a ratio of a wiring delay in a critical path delay time is reduced, thereby improving the operation speed.
Conventionally, the speed of a critical path including a long-distance wiring in a semiconductor integrated circuit device has been improved by (a) improvement of a load drive force of a gate circuit, (b) increase of width of the long-distance wiring, (c) dispersion of output load by gate circuit multiplication, and the like. When the ratio of a wiring delay in the critical path is small as compared to a delay time of the gate circuit, the speed increasing methods (a) to (c) can have a significant effect.
However, the effect of such methods (a) to (c) for increasing the speed becomes smaller as a semiconductor integrated circuit device increases its size and becomes finer. In a gate circuit method for driving all at once multi-fan out long-distance wiring having a large ratio of wiring delay in the critical path as compared to a gate circuit delay time, its output load is large and its output waveform becomes dull. Furthermore, after passing through the long-distance wiring, the waveform becomes greatly dull due to the wiring RC time constant. The reason of reduction of the effect of the methods (a) to (c) will be detailed below.
Method (a) can have a significant effect while the wiring resistance is sufficiently small as compared to the operation resistance of the load drive transistor of the gate circuit but the wiring resistance cannot be ignored as compared to the operation resistance of the load drive transistor of the gate circuit as the chip size becomes greater and the wiring becomes finer. Thus, method (a) can have an effect for the capacity load but cannot have a significant effect for the resistance load such as the wiring resistance. Method (b) is usually used together with method (a). That is, when method (b) is used to increase the wiring width and reduce the wiring resistance, the load capacity component is increased and accordingly, method (a) is used to increase the speed of the gate circuit for driving the long-distance wiring. However, when the wiring width is increased, although the wiring resistance is reduced, the wiring capacity is increased. Accordingly, the wiring delay time can be approximated by the product of the wiring resistance and the wiring capacity and the improvement of the wiring delay itself is not great. Furthermore, method (a) has a limitation from the viewpoint of the area overhead or the power consumption and the effect of increasing the speed is not sufficient. Method (c) or a technique of inserting a relay buffer in the middle of the long-distance wiring for increasing the speed also has a problem that two stages of inverter should be inserted for matching the signal polarity and increasing the speed in all cases is impossible due to the area problem.
As has been described above, increase of the wiring delay due to a long-distance wiring and the problem that a path passing through a gate circuit in the vicinity of the long-distance wiring end becomes a critical path go in the opposite direction against fine configuration of a semiconductor integrated circuit. This should be taken into consideration in future.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to suppress an area overhead, to reduce a ratio of a delay time caused by a wiring resistance in a critical path in a semiconductor integrated circuit, thereby increasing the speed of the critical path, and to increase the operation speed of a semiconductor integrated circuit device.
The present invention employs means as follows in order to achieve the aforementioned object.
The present invention provides a semiconductor integrated circuit device including a driver circuit
100
, a first long-distance wiring
104
connected to the driver circuit
100
, and a plurality of gate circuits
103
distributed over and connected to the entire length of the first long-distance wiring
104
, wherein an output signal of the driver circuit
100
is received via the first long-distance wiring
104
by the plurality of gate circuits
103
, and the driver circuit
100
has an input circuit connected to a node
105
in the vicinity of an input terminal of the gate circuit
103
connected to the end of the first long-distance wiring
104
using a second long-distance wiring
106
and a speed-increasing circuit
107
.
According to the present invention, in a gate circuit method for all-at-once driving multiple long-distance wiring fan-outs, a signal change is accelerated not only from one end of the driver circuit
100
but also from the other end by using a second long-distance wiring
106
and a speed-increasing circuit
107
from an early stage, thereby enabling to significantly reduce the wiring delay time and increase the critical path speed as well as to improve the operation speed of the semiconductor integrated circuit device. Moreover, since a waveform in the vicinity of the long-distance wiring end is driven by the speed-increasing circuit arranged physically in the vicinity, the waveform becomes sharp and a high-speed response of the receiver circuit can be obtained.
REFERENCES:
patent: 4849658 (1989-07-01), Iwamura et al.
patent: 6084800 (2000-07-01), Choi et al.
patent: 6088286 (2000-07-01), Yamauchi et al.
patent: 6271713 (2001-08-01), Krishnamurthy
patent: 6366520 (2002-04-01), Huber
patent: 6472917 (2002-10-01), Yamauchi et al.
patent: 2-165724 (1990-06-01), None
patent: 11-203858 (1999-07-01), None
patent: 11-317505 (1999-11-01), None
patent: 2000-058785 (2000-02-01), None
patent: 2000-243085 (2000-09-01), None
patent: 2000-268563 (2000-09-01), None
patent: 98/42021 (1998-09-01), None
Kuchimachi Kazuharu
Miyamoto Kazuhisa
Murabayashi Fumio
Takahashi Fumikazu
Yamauchi Tatsumi
Antonelli Terry Stout & Kraus LLP
Callahan Timothy P.
Cox Cassandra
Hitachi , Ltd.
LandOfFree
Semiconductor integrated circuit device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor integrated circuit device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3258885