Semiconductor integrated circuit device

Details Semiconductor integrated circuit device Semiconductor integrated circuit device

2002-08-21

2004-01-13

Zweizig, Jeffrey (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

Reexamination Certificate

active

06677803

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and, in particular, to a semiconductor integrated circuit device of low power consumption.
2. Description of the Related Art
In recent years, a steady progress has been made in enhancing high packing density and high performance of LSIs and the field of application of the LSIs have been expanded. In accordance with the expansion of the field of application, technical challenges such as reducing the power consumption of the LSI and increasing the operating speed of the circuit of the LSI are presented. In a CMOS-LSI, the power consumption is proportional to the square of a power supply voltage and thus reducing the power supply voltage is the most effective means for reducing the power consumption. However, if the power supply voltage is reduced, the operating speed of the CMOS-LSI is reduced. Therefore, in order to keep the operating speed, the threshold voltage of a MOS transistor needs to be reduced. Reducing the threshold voltage leads to a problem of increasing a leakage current caused by the sub-threshold current of the MOS transistor in a static operation. In order to solve this problem, a Dynamic Threshold Metal Oxide Semiconductor (hereinafter referred to as DTMOS) is proposed in which the threshold voltage of the MOS transistor is dynamically varied, thereby to reduce a leakage current in the static operation and to realize a high speed operation. For example, as a paper to describe the result of research using a DTMOS as a SOI device, there is an article titled “SOI Technology Performance and Modeling” authored by J. L. Pelloie, A. J. Auberton-Herv, C. Raynaud, O. Faynot, IEEE, WP25.2, 1999.
In
FIG. 14
, a circuit of a DMOS-NMOS transistor with a transistor for limiting a body voltage in the related art, which is described in the above article, is shown. This DTMOS transistor in the related art is constituted by: an NMOS transistor N
1
in which a node
1
of an input terminal is connected to a gate, a node
2
of a GND line is connected to a source, and a node
3
is connected to a drain; and an NMOS transistor N
2
in which a node
4
is connected to a power supply line is connected to a gate, the node
1
is connected to a drain (or a source), and a node
5
of the body of the NMOS transistor N
1
is connected to a source (or a drain). In the DTMOS transistor in the related art, as shown in
FIG. 14
, the NMOS transistor N
2
prevents a voltage larger than a built-in voltage (for example, 0.8 V) from being applied to the node
5
which is a back (substrate voltage terminal) of the NMOS transistor N
1
in other words, acts as a “limiter” of preventing a voltage larger than the built-in voltage from being applied to a body voltage terminal. For this reason, a junction leakage current passing through the node
5
and the node
2
can be reduced. Although not described in the above article, also the DTMOS-PMOS transistor with a transistor for limiting a body voltage, shown in
FIG. 15
, can produce the same effect as an NMOS type DTMOS transistor circuit.
However, since the electric potential of the body of the NMOS transistor N
2
is not fixed at a GND level in the DTMOS-PMOS transistor with a transistor for limiting a body voltage in the related art shown in
FIG. 14
, if a large voltage (for example, 1.5 V) is applied across the source and the drain, holes generated by an impact ionization phenomenon generated in the vicinity of the drain of the NMOS transistor N
2
are flowed into a portion (hereinafter referred to as a body region) in the vicinity of a buried oxide film under a gate channel to increase the electric potential of the body region. As a result, this increases the junction leakage current between the body of the NMOS transistor N
2
and the node
5
or the node
1
of the NMOS transistor N
1
. This results in presenting a problem that a current consumption is increased in the static operation. The current-voltage characteristics of the NMOS transistor N
2
are shown in
FIG. 18A
, in which the drain current is increased by the phenomenon described above when the drain voltage is large. Similarly, the current-voltage characteristics of the PMOS transistor P
2
are shown in
FIG. 18B
, in which a drain current is increased by the phenomenon described above when a drain voltage is large.
In
FIG. 16
, an inverter circuit constituted by one NMOS type DTMOS transistor with a function for limiting a body voltage and one PMOS type DTMOS transistor with a function for limiting a body voltage in the related art is shown. This inverter circuit constituted by the DTMOS transistors in the related art is constituted by: an NMOS transistor N
1
in which a node
1
of an input terminal is connected to a gate, a GND line is connected to a source, and a node
2
is connected to a drain of an output; an NMOS transistor N
2
in which a power supply line is connected to a gate, the node
1
is connected to a drain (or a source), and a node
3
of the body of the NMOS transistor N
1
is connected to a source (or a drain) ; a PMOS transistor P
1
in which the node
1
of an input terminal is connected to a gate, the power supply line is connected to a source, and the node
3
is connected to a drain of an output; and a PMOS transistor P
2
in which the GND line is connected to a gate, the node
1
is connected to a drain (or a source), and a node
4
of the body of the PMOS transistor P
1
is connected to a source (or a drain).
In
FIG. 17
, the operation waveforms of the node
1
, the node
2
, the node
3
and the node
4
of the DTMOS inverter circuit shown in
FIG. 16
are shown. A voltage larger than the built-in voltage is applied as an input voltage. When the node
1
is at the GND level (that is, the electric potential of the node
1
is GND) at a time T
1
, both of the NMOS transistor N
1
and the NMOS transistor N
2
are in the OFF state and both of the PMOS transistor P
1
and the PMOS transistor P
2
are in the ON state. Therefore, the node
2
and the node
3
are set at the power supply (voltage) level. The voltage of the node
4
is limited by the PMOS transistor P
2
and thus the node
4
is set at the built-in voltage level.
During a period of time from T
2
to T
3
, while the voltage of the node
1
gradually reaches from the GND level to the power source level, the NMOS transistor N
1
and the NMOS transistor N
2
gradually reach the state of ON and the PMOS transistor P
1
gradually reach the state of OFF. During this period of time, the node
3
being at the power source level gradually reaches to the GND level. Further, because the PMOS transistor P
2
is in the ON state, as the node reaches a VDD level, the node
4
is increased gradually to the VDD level.
At the time T
4
, when the node
1
is at the VDD level, the NMOS transistor N
1
and the NMOS transistor N
2
are in the ON state and the PMOS transistor P
1
and the PMOS transistor P
2
are in the OFF state. At this time, the node
2
and the node
4
are at the GND level. The voltage of the node
3
is limited by the NMOS transistor N
2
and thus the node
3
is set at the built-in voltage level when viewed from the VDD level.
During a period of time from T
5
to T
6
, while the voltage of the node
1
gradually reaches from the power source level to the GND level, the NMOS transistor N
1
and the NMOS transistor N
2
gradually reach the state of OFF and the PMOS transistor P
1
and the PMOS transistor P
2
gradually reach the state of ON. During this period of time, because the NMOS transistor N
2
is in the ON state, as the node
1
reaches the GND level, the node
3
being at the built-in voltage level is gradually lowered to the GND level.
Here, at the time T
3
, the node
1
is at the VDD level and the node
3
is at the built-in voltage level, so the potential difference between the node
1
and the node
3
, that is, the potential difference between the source and the drain of the NMOS transistor N
2
is equal to the difference between the power source level

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