Computer graphics processing and selective visual display system – Computer graphics processing – Three-dimension
Reexamination Certificate
2000-05-05
2004-04-27
Zimmerman, Mark (Department: 2671)
Computer graphics processing and selective visual display system
Computer graphics processing
Three-dimension
Reexamination Certificate
active
06727900
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device provided with a memory and a three-dimensional graphics processing circuit.
BACKGROUND ART
The Z buffering process is a typical example of the hidden surface removal process for a three-dimensional graphics. According to this process, each pixel is made to have a distance (Z value: depth data) from an eye point, Z values are compared during depiction, and only a shallowest pixel (having a smallest Z value) is displayed among a plurality of pixels having the same coordinate. According to this process, a shallowest image on a screen is preferentially displayed and an image hidden behind the shallowest image is not displayed.
Currently, a three-dimensional graphics frame buffer memory including a necessary circuit for such Z buffering process together with a memory on one chip has been provided. Details of the memory are disclosed in U.S. Pat. No. 5,673,422 (Japanese Patent Laying-Open No. 7-249116); Nakamura, Inoue and Kawai, ‘Three-dimensional Graphics Frame Buffer Memory (3D-RAM)’, Mitsubishi Electronics Technological Review, Vol. 69, No. 3, 1995, pp42-46; and U.S. Pat. No. 5,544,306.
The frame buffer memory includes a comparison unit comparing a Z value supplied from an external source for a new image and a Z value already stored in the memory for a current image, and thereby allows Mostly-Write operation instead of Read-Modify-Write operation in which a Z value of a currently displayed image is read from the memory and compared with a Z value of a new image whenever the new image is to be displayed, and data of a shallower image is written into the memory.
Even such frame buffer memory with the comparison unit, however, takes a long time for the Z buffering process because a Z value must be input from an external source for each pixel. In addition, when the Z value supplied from the external source indicates a deep point on a screen, the input of such Z value is useless because the Z value will not be stored in the memory after all.
DISCLOSURE OF INVENTION
An object of the present invention is to provide a semiconductor integrated circuit device capable of a high-speed Z buffering processing.
The semiconductor integrated circuit device according to the present invention includes a memory and a detection circuit. The memory stores depth data of each of pixels forming a three-dimensional graphics image. The detection circuit detects depth data representing a deepest point on the three-dimensional graphics image among depth data stored in a predetermined region of the memory for a plurality of pixels.
Preferably, the semiconductor integrated circuit device further includes a terminal for supplying the depth data detected by the detection circuit as an output from the device.
Hence, a main advantage of the present invention lies in that the Z buffering process can be performed faster than in a case where depth data is compared for each pixel, because depth data representing a deepest point among depth data for the plurality of pixels is detected.
Further, another advantage of the present invention is that input of data other than depth data eventually written into the memory are prevented and a useless input of depth data can be avoided because depth data representing a deepest point is detected and supplied as an output from the device.
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McDermott & Will & Emery
Renesas Technology Corp.
Santiago Enrique L
Zimmerman Mark
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