Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2002-02-04
2003-04-22
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Addressing
Sync/clocking
Reexamination Certificate
active
06552958
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device such as a processor, which provides dynamic or static control of the operating clock frequency of internal modules of the device by supplying clock signals and clock sync signals thereto, in order to reduce the power consumption.
2. Description of the Related Art
A conventional method for reducing the power consumption of a processor operating on the basis of internal clocks is to perform the stepwise frequency dividing of a reference clock signal to produce a modified clock frequency. In order to carry out the conventional method, a clock sync signal for masking an internal clock in accordance with the highest internal clock speed is supplied or the frequency dividing of the internal clock is performed.
With recent developments of high-speed processors and their large-scale integration, the clock control by supplying a clock signal with a controlled clock frequency to each internal module of the processor has become an important method for providing reduction of power consumption during a time when high-speed processing is not needed.
However, the conventional method has the basic restriction that the clock speed of a controlling module of a processor (for example, a memory controller) must be higher than or equal to the clock speed of a controlled module (for example, a memory). Hence, according to the conventional method, it is difficult to use the clock speed of the controlling module lower than the clock speed of the controlled module in order to provide reduced power consumption when high-speed processing is not needed.
For example, suppose that a processor is provided with an SDRAM (synchronous dynamic random access memory) as a controlled external peripheral module and the processor includes an SDRAM controller as a controlling internal module thereof. The SDRAM is designed to work at the clock speed 133 MHz. In such a case, the basic restriction for the SDRAM controller of the processor to properly control the external SDRAM is that the SDRAM controller must work at the clock speed that is equal to a multiple of 133 MHz. In the clock line of the processor, which is connected to the external SDRAM for sending the clock signal thereto, a PLL (phase-locked loop) circuit or a DLL (delay-locked loop) circuit is usually provided for the phase matching between an internal clock of the processor and a clock signal supplied to the external SDRAM. It is necessary to maintain the operating clock frequency of the clock signal supplied to the SDRAM at a constant level (for example, 133 MHz).
In the above case, if the operating clock frequency of the clock signal supplied to the SDRAM is changed to a lower clock frequency (for example, 33 MHz), in order to provide a reduction of the power consumption of the SDRAM controller in the processor, the PLL circuit provided in the SDRAM clock line is set in an unlocked state. A certain period of the waiting time is required until the PLL circuit is returned to the locked state again, and during the waiting time data transfer between the processor and the external SDRAM cannot be performed. Further, if the operating clock frequency of the clock signal supplied to the SDRAM is maintained at the lower clock speed 33 MHz, the performance of the entire system will deteriorate.
As described above, according to the conventional method, it is difficult to use the clock speed of the controlling module lower than the clock speed of the controlled module in order to reduce power consumption when the high-speed processing is not needed.
Moreover, when designing a high-speed processor, the method for preventing the skewing of the clock signals between the internal modules of the processor has become increasingly important. As the clock speed of the processor increases and the scale of the circuit integration becomes larger, it is difficult to prevent the skewing of the clock signals between the internal modules. Specifically, when determining the layout of the processor, the number of clock buffers or the length of the clock lines is adjusted in accordance with the arrangement of individual internal modules so as to prevent the skewing of the clock signals between the internal modules. It is also necessary to perform the timing adjustment related to clock skewing.
In summary, the conventional method has the following problems. First, it is difficult to synchronize the data transfer between the controlling module and the controlled module if the clock speed of the controlling module lower than the clock speed of the controlled module is used in order to reduce the power consumption when the high-speed processing is not needed. Second, as the scale of the circuit integration becomes larger, it is difficult to prevent the skewing of the clock signals between the internal modules of the processor.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an improved semiconductor integrated circuit device in which the above-described problems are eliminated.
Another object of the present invention is to provide a semiconductor integrated circuit device which reliably keeps synchronization of the data transfer between the internal modules even when the operating clock frequency is changed to a lower clock frequency.
Another object of the present invention is to provide a semiconductor integrated circuit device which is capable of preventing the skewing of the clock signals between the internal modules thereof.
The above-mentioned objects of the present invention are achieved by a semiconductor integrated circuit device comprising: a first circuit which has a clock generating circuit generating a clock signal; and a second circuit which receives the clock signal from the clock generating circuit, wherein the first circuit maintains a frequency of the clock signal at a fixed frequency when an operating clock frequency of the first circuit is changed to another clock frequency, and the first circuit supplies a control signal and the clock signal to the second circuit so that an operating clock frequency of the second circuit is determined based on a combination of the control signal and the clock signal.
The above-mentioned objects of the present invention are achieved by a semiconductor integrated circuit device comprising: a clock control unit which generates a first internal clock and a second internal clock based on an externally generated input clock signal, and generates a first clock sync signal and a second clock sync signal based on a result of comparison of a frequency of the first internal clock and a frequency of the second internal clock; and a first module which receives the first internal clock and the first and second clock sync signals and includes an internal circuit which generates a clock enable signal used to control an operating clock frequency of a second module that operates on the basis of the frequency of the second internal clock, wherein the semiconductor integrated circuit device synchronizes data transfer between the first module and the second module, regardless of whether an operating clock frequency of the first internal clock is changed to another clock frequency, by supplying the clock enable signal to the second module.
The above-mentioned objects of the present invention are achieved by a semiconductor integrated circuit device comprising: a clock control unit which generates a variable-frequency first clock signal and a first clock sync signal; and a first circuit which receives the first clock signal and the first clock sync signal and generates a fixed-frequency second clock signal and a second clock sync signal that are supplied to a second circuit, the first circuit and the second circuit performing data transfer between the first circuit and the second circuit, wherein the semiconductor integrated circuit device synchronizes, when a frequency of the first clock signal is lower than a frequency of t
Satoh Taizoh
Shikata Takashi
Fujitsu Limited
Nguyen Tan T.
Staas & Halsey , LLP
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