Semiconductor integrated circuit device

Details Semiconductor integrated circuit device Semiconductor integrated circuit device

2001-02-20

2003-12-16

Toatley, Jr., Gregory J. (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

C361S111000, C361S117000, C361S118000, C361S119000

Reexamination Certificate

active

06665159

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device and, more particularly, to a technique which is effective when applied, in a semiconductor integrated circuit device including circuits for processing signals from an intermediate-frequency band to a high-frequency band, to a protective technique for preventing the electrostatic breakdowns of circuit elements constructing the semiconductor integrated circuit device.
A wireless communication system (or a wireless communication mobile terminal device, as will be shortly called the “terminal device”) such as a digital cellular system has its circuits of transmission line and reception line constructed to include many discrete ICs (semiconductor integrated circuit devices). A representative example of the terminal device, of which the transmission/reception line circuits are constructed of the discrete ICs, is shown in FIG.
9
. The discrete ICs are serviced from semiconductor parts makers such as NEC or RF Micro Device.
On the other hand, the technique of integrating the transmission/reception units into one chip is described on pp. 17 to 20 of “Hitachi Review”, Vol. 81, No. 10 (1999-10), issued by Hitachi Reviewer Co., Ltd.
On the other hand, the electrostatic breakdown protecting circuit of IC is disclosed in Japanese Patent Laid-Open No. 230266/1989, for example. In this Laid-Open, there is disclosed an electrostatic breakdown preventing circuit in which a plurality of diodes are connected in series between the terminal of an integrated circuit and a power supply line or a ground line.
In Japanese Patent Laid-Open No. 202583/1995, on the other hand, there is disclosed a CMOS protective circuit corresponding to the CMOS circuit in which a plurality of power supply voltages are mixed.
Here will be described the prior art with reference to the accompanying drawings.
FIG. 9
is a schematic block diagram showing transmission/reception circuits or the like, which are packaged in the terminal device of the prior art. The ICs are individually made functionally discrete, and the portions, as individually enclosed by squares, are the discrete ICs.
In this block diagram, there are shown a transmission line and a reception line, which are connected with an antenna
1
through a duplexer
2
. Both these transmission line and reception line are connected with the not-shown base band.
The reception line is constructed by connecting the antenna
1
, a band-pass filter
3
packaged in the duplexer
2
, a low-noise amplifier
4
, a band-pass filter
5
, a reception mixer
6
, a band-pass filter
7
, a variable-gain controlled amplifier
8
and a demodulator
9
sequentially in series. The demodulator
9
is connected with the not-shown base band.
The transmission line is constructed by connecting a modulator
11
, a variable-gain controlled amplifier
12
, a transmission mixer
13
, a band-pass filter
14
, a transmission preamplifier
15
, a high-output amplifier
16
, a band-pass filter
17
packaged in the duplexer
2
, and the antenna
1
sequentially in series. The modulator
11
is connected with the not-shown base band. On the other hand, the demodulator
9
and the modulator
11
perform the frequency conversion in response to a station signal inputted from a VCO
18
. The reception mixer
6
and the transmission mixer
13
also perform the frequency conversion in response to the station signal from a VCO
19
.
The signals (in electric waves)
10
, as received by the antenna
1
, are sequentially processed by the individual circuits of the reception line and are sent to the base band. On the other hand, the signals, as sent from the base band, are sequentially processed by the individual circuits of the transmission line and are emitted as the electric waves
10
from the antenna
1
.
The portions, as enclosed by the squares, are the discrete ICs, as has been described hereinbefore. On the other hand, the internal small squares are electrostatic breakdown protecting circuits
20
(as will be called the “protective circuits”).
In the construction of the prior art thus far described, it is estimated from the handling notices described in the IC catalogue of each semiconductor parts maker that the variable-gain controlled amplifiers
8
and
12
, the demodulator
9
and the modulator
11
, or the intermediate-frequency band ICs of several hundreds MHz are provided with the protective circuits
20
for preventing the circuit breakdowns, as might otherwise be caused by the electrostatic charges from several tens to several hundreds V, to enhance the high breakdown voltages.
On the other hand, the high-frequency band ICs in the vicinity of 1 GHz such as the low-noise amplifier
4
, the reception mixer
6
, the transmission mixer
13
, the transmission preamplifier
15
or the high-output amplifier
16
are described for the user to consider the static electricities, and it is also estimated that no protective circuit is included.
As one example of the protective circuit, there is known a protective circuit which is disclosed in Japanese Patent Laid-Open No. 202583/1995, as described hereinbefore.
FIG. 10
is a schematic diagram in which a portion is added for easier illustration to the diagram of the protective circuit presented by the Laid-Open.
In
FIG. 10
, numeral
41
designates a protective circuit. Letter V designates an input or output signal to an integrated circuit, and this signal is inputted via a signal line
44
to an internal circuit
45
or outputted from the internal circuit
45
. The protective circuit
41
is made of a diode-connected NMOS transistor
42
and an NMOS transistor
43
. Specifically, the transistor
42
is connected at its shorted gate and drain with the signal line
44
and is connected at its source with a power supply voltage Vcc. On the other hand, the transistor
43
is connected at its drain with the signal line
44
and at its shorted gate and source with the ground.
On the other hand, one example of the protective circuit having diodes connected at multiple stages is disclosed in Japanese Patent Laid-Open No. 230266/1989, as has been described hereinbefore.
FIGS. 11 and 12
are schematic diagrams in which a portion is added to the diagrams of the diodes for forming the protective circuit and the electrostatic breakdown preventing circuit of that Laid-Open, so as to facilitate the description.
As shown in
FIG. 11
, two diodes
51
and
52
are connected in series at two stages in the forward direction between the signal line
53
and the ground line
55
of an internal circuit
54
. A signal is transmitted via the signal line
53
to the internal circuit
54
.
FIG. 11
omits the protective circuit on the power supply side, the action of which is identical to that shown in FIG.
10
.
By the two-stage construction, a Von voltage is raised to suppress the electric current to flow through the protective circuit.
FIG. 12
shows a sectional structure of the protective circuit elements constructed to have a two-stage connection. Over one face of a P-type substrate
61
forming an integrated circuit, there is formed an N-type epitaxial layer
62
. On the surface side of this N-type epitaxial layer
62
, there are formed a plurality of (or two, as shown) P-type diffusion layers
63
for wells. In the surface layer portion of the P-type diffusion layer
63
, on the other hand, there is formed an N-type diffusion layer
64
. Therefore, the P-type diffusion layer
63
and the N-type diffusion layer
64
form PN junction diodes (
51
and
52
).
Between the individual P-type diffusion layers
63
, on the other hand, there is formed a P-type insulating diffusion layer
65
as a channel stopper. This P-type isolating diffusion layer
65
so extends all over in the thickness direction of the N-type epitaxial layer
62
as to reach the P-type substrate
61
at is lower end.
Over the surface on one side of the P-type substrate
61
, on the other hand, there is formed a silicon dioxide film
66
. This silicon dioxide film
66
is partially removed at its portion co

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