Semiconductor integrated circuit device

Details Semiconductor integrated circuit device Semiconductor integrated circuit device

2001-10-26

2003-09-16

Mis, David C. (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

C331S025000, C331SDIG002, C331S044000, C327S156000, C327S159000

Reexamination Certificate

active

06621352

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and particularly to the technology that can be effectively applied to the measuring technique for semiconductor integrated circuit devices provided with a clock generating circuit for generating an internal clock signal corresponding to the clock signal which is supplied from an external terminal.
2. Description of the Related Art
The search for references after application of the present invention has reported that an integrated circuit with PLL circuit provided with a jitter measuring circuit is disclosed in Japanese laid-open patent JP-A No. 2000-35463, an integrated circuit with PLL circuit provided with a detection circuit for evaluating jitter is disclosed in Japanese laid-open patent JP-A No. H6-104746, an integrated circuit with PLL circuit provided with a test circuit for calculating a lock time is disclosed in Japanese laid-open patent JP-A No. H11-2666, an integrated circuit provided with a frequency measuring circuit is disclosed in Japanese laid-open patent JP-A No. H11-23662 and an integrated circuit with PLL circuit provided with a frequency measuring circuit is disclosed in Japanese laid-open patent JP-A No. H9-197024.
Researches are aided to improvement in the operation rate of a circuit with advancement of the semiconductor technology. For example, in a semiconductor integrated circuit device for data input/output operation synchronized with the clock signal of the frequency of 500 MHz or higher, an occupation rate of delay of signal in an input circuit for fetching, to the integrated circuit, the clock signal inputted from an external terminal for the clock period can not be neglected. An internal clock signal having compensated for signal delay in the input circuit can be formed with use of a PLL circuit or DLL circuit.
Circuit elements formed in a semiconductor integrated circuit has comparatively large fluctuation in process. On the occasion of comprising a PLL or DLL circuit as explained above and forming an internal clock signal of high frequency as explained above, it can be thought that measurement to determine whether such clock signal should satisfy the desired frequency, phase or jitter characteristic or the like is now indispensable. Therefore, it can also be thought to use a high precision analog tester but in this case, an exclusive high-speed input/output circuit including the measuring terminals is required and moreover highly accurate determination becomes difficult even when an expensive measuring circuit is used because a signal delay in such input/output circuit becomes a serious problem. In addition, in the measuring circuit described in the above official gazettes, measurement accuracy is low and such measuring circuit is inadequate for PLL or DLL circuit which operates even in such higher frequency.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor integrated circuit device that has realized verification with higher accuracy of a plurality of operations for a clock generating circuit to form an internal clock signal. Another object of the present invention is to provide a semiconductor integrated circuit device that has enabled, through simplification of a structure, verification of various performances of an internal clock signal generating circuit. The abovementioned and other objects and novel characteristics of the present invention will be become more apparent from description of this specification and accompanying drawings thereof.
Typical inventions among those disclosed in this specification will be outlined below. For the clock generating circuit to form an internal clock signal corresponding to an input clock signal inputted from an external terminal, a measuring circuit for measuring at least two or more items among the lock time until the desired internal clock signal corresponding to the input signal is obtained, the maximum frequency of the internal clock signal and the jitter of the internal clock signal is provided in order to execute, with higher accuracy, verification for operations of the clock generating circuit in the semiconductor integrated circuit.


REFERENCES:
patent: 6-104746 (1992-09-01), None
patent: 9-197024 (1996-01-01), None
patent: 11-2666 (1997-06-01), None
patent: 11-23662 (1997-07-01), None
patent: 2000-35463 (1998-07-01), None
patent: 2002-131389 (2002-05-01), None

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