Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Field effect transistor
Reexamination Certificate
2000-08-16
2003-01-14
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
Field effect transistor
C257S192000, C257S195000, C257S402000, C257S409000, C438S167000, C438S172000, C438S176000
Reexamination Certificate
active
06507051
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor integrated circuit devices including field-effect transistors, and more particularly to an integrated high-breakdown-voltage compound semiconductor field effect transistor.
2. Description of the Related Art
A compound semiconductor field effect transistor (FET) is known as a high-frequency device. Typically, such a compound semiconductor FET is a high electron mobility field effect transistor (HEMT) and a Schottky gate type field effect transistor (MESFET). When the FETs as described above are used as power devices, these FETs are required to have a high breakdown voltage. One of the factors involved in the breakdown voltage of the FETs is a phenomenon in which the electric field is locally raised in a portion of the gate electrode close to the drain end (generally, the above is called electric field concentration). Particularly, in the ON state, the electric field exceeds the critical value which causes impact ionization at the drain end of a depletion layer extending from the gate electrode, so that an Avalanche breakdown is caused.
As means for relaxing the electric field concentration, there are known a dual-gate structure and a groove which is formed between the gate and drain. In any means, the depletion layer or the groove extends in the depth direction from the surface between the gate and the drain. This arrangement narrows the current path through which the drain current flows and increases the voltage drop developing across the narrowed current path. This decreases the potential of the gate electrode at the drain end. Consequently, the electric field intensity is lowered.
The dual-gate structure has the following disadvantages. The depletion layer in the dual-gate structure has a larger capacitance than that of the single-gate structure because the dual-gate structure has two gates. An increase in the capacitance of the depletion layer increases parasitic capacitance and thus degrades the high-frequency characteristics.
The use of the groove formed between the gate and the drain increases the ON resistance because of the narrowed current path below the groove and thus reduces the gain.
As described above, the conventional high-frequency compound semiconductor field effect transistors, which are typically HEMT and MESFET, do not have good high-frequency characteristics because of the arrangement directed to avoiding the electric field concentration and obtaining an increased breakdown voltage. In other words, the conventional FETs do not realize the high-breakdown voltage and the good high-frequency characteristics simultaneously.
SUMMARY OF THE INVENTION
It is a general object of the present invention to provide a semiconductor integrated circuit device in which the above-mentioned disadvantages are eliminated.
A more specific object of the present invention is to provide a semiconductor integrated circuit device which has an improved the high-breakdown voltage and an improved high-frequency characteristics.
The above objects of the present invention are achieved by a semiconductor device comprising: a semiconductor layer structure; gate, drain and source electrodes being provided on the semiconductor layer structure, the gate electrode being located between the drain and source electrodes; and a depletion modulating part that is located between the gate electrode and the drain electrode and includes portions spaced apart from each other in a gate-width direction.
The above objects of the present invention are also achieved by a semiconductor device comprising: cap layers that make ohmic contacts with a source electrode and a drain electrode and defines a gate recess; a gate electrode in the gate recess; and a continuous layer that is provided on a semiconductor surface between the gate electrode and one of the cap layers which makes an ohmic contact with the drain electrode, the continuous layer being electrically conductible with respect to the semiconductor surface and continuously extending in a gate width direction.
REFERENCES:
patent: 404125973 (1992-04-01), None
Armstrong Westerman & Hattori, LLP
Fujitsu Limited
Kang Donghee
Loke Steven
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