Semiconductor integrated circuit device

Details Semiconductor integrated circuit device Semiconductor integrated circuit device

1998-10-23

2002-10-29

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C327S545000, C327S427000

Reexamination Certificate

active

06472930

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, especially to a current generator preventing its output ringing.
2. Background of the Invention
A converter for converting a signal from digital to analog (hereinafter referred to as “D/A converters”), especially a current output type D/A converter, is an aggregate of current generators each including 2
N−1
constant current sources for N input digital bits and outputting current corresponding to the number of input digital bits. In the following, the structure of a typical D/A converter and problems thereof will be described.
First, we will describe the structure of a typical D/A converter
90
with reference to FIG.
30
. The D/A converter
90
is mainly composed of a plurality of current source cells CL, and moreover includes a decoder/clock buffer portion DB connected to the current source cells CL, a bias circuit BC, and so on. Each of the current source cells CL has two output nodes I
1
and I
2
connected to output terminals IT and {overscore (IT)}, respectively. The output terminal IT is grounded via an external resistance R
2
, and the output terminal {overscore (IT)} is directly grounded.
Next, we will describe the structure of the current source cell CL that is composed of a current generator CG and a driver circuit DC.
The current generator CG is composed of P-channel MOSFETs, including a constant-current-source transistor M
1
connected at its source electrode to a power supply VDD, for generating constant current in response to a bias signal BS applied from the bias circuit BC, and transistors M
2
and M
3
each connected at its source electrode to a drain electrode of the transistor M
1
. The drain electrodes of the transistors M
2
and M
3
correspond to the output nodes I
1
and I
2
, respectively. On receipt of control signals from the driver circuit DC, the transistors M
2
and M
3
complementarily operate to function as current switches (first and second switch means).
The driver circuit DC is composed of inverter circuits IV
2
and IV
3
connected at their outputs to the transistors M
2
and M
3
, respectively. The inverter circuit IV
2
comprises a P-channel transistor M
6
and an N-channel transistor M
7
connected in series between the power supply VDD and the ground, and each receiving a selection signal SL at its gate electrode. The inverter circuit IV
3
comprises a P-channel transistor M
8
and an N-channel transistor M
9
connected in series between the power supply VDD and the ground, and each receiving a selection signal {overscore (SL)} at its gate electrode. The selection signals SL and {overscore (SL)} are applied from a decoder of the decoder/clock buffer portion DB.
The current-output type D/A converter
90
with such a structure has faced a problem that recent high speed in D/A conversion increases variations in output current per unit of time, thereby causing ringing in the output waveform.
FIG. 31
shows such an output waveform with ringing. The horizontal axis indicates time, and the vertical axis indicates an output voltage. As shown, ringing mostly occurs on the top portion that is originally supposed to be flat and near the falling edge of the output waveform. As a fluctuation in the output waveform, the ringing must be reduced at any cost to secure the quality of the analog output.
Referring to
FIG. 32
, we will now describe the cause of the ringing.
FIG. 32
shows inductance components and capacitive components, which are parasitic on the D/A converter
90
in
FIG. 30
, as inductance and capacitance, respectively.
As shown in
FIG. 32
, there are parasitic inductance L
1
between the power supply VDD and the source electrode of the transistor M
1
(connected to a power terminal PT), parasitic capacitance C
3
between the source electrode of the transistor M
1
and the drain electrode of the transistor M
2
, parasitic capacitance C
4
between the source electrode of the transistor M
1
and the drain electrode of the transistor M
3
, parasitic capacitance C
5
between the drain electrode of the transistor M
2
and a substrate SS, and parasitic capacitance C
6
between the drain electrode of the transistor M
3
and the substrate SS.
Further, there are parasitic inductance L
2
between the output terminal IT and the external resistance R
2
, parasitic inductance L
3
between the output terminal {overscore (IT)} and the ground GND, and parasitic capacitance C
2
in parallel with the external terminal R
2
.
The ringing is caused by a resonance of the parasitic inductance and the parasitic capacitance. Especially, it is considerably enlarged in the presence of the circuit that includes only the parasitic inductance and the parasitic capacitance on its path from the power supply VDD to the ground GND, or in the presence of a loop circuit that is composed only of the parasitic inductance and the parasitic capacitance.
As an example of the circuit that includes only the parasitic inductance and the parasitic capacitance on its path from the power supply VDD to the ground GND, a first LC circuit PS
1
is shown in bold type in FIG.
33
. This circuit is composed of the power supply VDD, the parasitic inductance L
1
, the parasitic capacitance C
4
, the parasitic inductance L
3
, and the ground GND.
FIG. 33
, given for explanation of this circuit, is basically the same as FIG.
32
.
As another example of such a circuit, a second LC circuit PS
2
is shown in bold type in FIG.
34
. This circuit is composed of the power supply VDD, the parasitic inductance L
1
, the parasitic capacitance C
3
, the parasitic inductance L
2
, the parasitic capacitance C
2
, and the ground GND.
FIG. 34
, given for explanation of this circuit, is basically the same as FIG.
32
.
As an example of the loop circuit that is composed only of the parasitic inductance and the parasitic capacitance, third and fourth circuits PS
3
and PS
4
are shown in bold type in FIG.
35
. The third circuit PS
3
is composed of the substrate SS, the parasitic capacitance C
5
, the parasitic inductance L
2
, the parasitic capacitance C
2
, and the ground GND, and the fourth circuit PS
4
is composed of the substrate SS, the parasitic capacitance C
6
, the parasitic inductance L
3
, and the ground GND. If a P-type semiconductor substrate is used, these two circuits are looped because the substrate potential becomes the ground potential.
FIG. 35
, given for explanation of the third and the fourth circuits, is basically the same as FIG.
32
.
This ringing problem has not been characteristic of the current generator in the D/A converter, but common to the semiconductor integrated circuit devices with similar structures.
SUMMARY OF THE INVENTION
A first aspect of the present invention is directed to a semiconductor integrated circuit device comprising: a constant current source connected to a first power supply via a power terminal; first and second current switches connected to the output of the constant current source in parallel with each other, for outputting the output of the constant current source complementarily as first and second outputs respectively on the basis of first and second control signals complementarily applied from driving means; first and second terminals receiving the first and the second outputs, respectively; a first resistive element provided on at least either one of a first path connecting the first current switch and the first terminal and a second path connecting the second current switch and the second terminal.
Preferably, according to a second aspect of the present invention, the first terminal outputs the first output to the outside as the output of the semiconductor integrated circuit device; the second terminal connects the second output to a second power supply; and the first resistive element is provided on the second path.
Preferably, according to a third aspect of the present invention, the first terminal outputs the first output to the outside as the output of the semiconductor integrated circuit device; the seco

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