Semiconductor integrated circuit device

Details Semiconductor integrated circuit device Semiconductor integrated circuit device

1999-09-23

2002-02-05

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Amplitude control

C326S068000, C326S081000

Reexamination Certificate

active

06344764

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device having a level-shifting circuit for shifting the signal amplitude.
In some semiconductor integrated circuit devices, a circuit using different voltages to input/output signals of different voltage levels is integrated in one chip. Such device incorporates a level-shifting circuit to shift, e.g., a power supply voltage level to another voltage level.
In semiconductor storage devices such as a DRAM, SRAM, and flash memory, many memory peripheral circuits use a power supply voltage to output a signal of the power supply voltage level. Of the memory peripheral circuits, e.g., a circuit for driving word lines uses a boosted voltage higher than the power supply voltage to output a signal of the boosted voltage level in order to accurately read out data of a memory cell. The level-shifting circuit shifts a signal of the power supply voltage level to a signal of the boosted voltage level.
Recently in the semiconductor storage device field, the power supply voltage is being reduced to reduce power consumption. However, the word line driving circuit must accurately read out data of a memory cell. Thus, the boosted voltage is more difficult to reduce than the power supply voltage, and the ratio of the power supply voltage to the boosted voltage is increasing. Owing to this trend, it is becoming difficult for the level-shifting circuit to output an input signal of the power supply voltage level as an output signal of the boosted voltage level.
FIG. 1A
is a circuit diagram showing a conventional level-shifting circuit, and
FIG. 1B
is a waveform chart showing operation of this circuit.
The arrangement and operation of the level-shifting circuit will be described.
When an input signal IN
101
changes from “L” level to “H” level at time T
1
shown in
FIG. 1B
, a power supply potential VCC is input to the gate of an n-channel transistor QN
102
to turn on the transistor QN
102
. Since the transistor QN
102
is turned on, the potential of a node N
102
drops to turn on a p-channel transistor QP
1
O
1
. At this time, a ground potential VSS is input to the gate of an n-channel transistor QN
101
, so the transistor QN
101
is OFF. The potential of a node N
101
changes to a boosted potential VPP to change an output signal OUT
101
to “H” level. Since the potential of the node N
101
changes to the boosted potential VPP, a p-channel transistor QP
102
is turned off. Then, the potential of the node N
102
changes to the ground potential VSS (note that the potential of the node N
102
in the circuit shown in
FIG. 1A
is “VSS−VTH”: VTH is the threshold voltage of the transistor QN
102
).
When the input signal IN
101
changes from “H” level to “L” level at time T
2
, the power supply potential VCC is input to the gate of the transistor QN
101
to turn on the transistor QN
101
. Since the transistor QN
101
is turned on, the potential of the node N
101
drops to turn on the transistor QP
102
. At this time, the ground potential VSS is input to the gate of the transistor QN
102
, so the transistor QN
102
is OFF. The potential of the node N
102
changes to the boosted potential VPP. Since the potential of the node N
102
changes to the boosted potential VPP, the transistor QP
101
is turned off. Then, the potential of the node N
101
changes to the ground potential VSS (note that the potential of the node N
101
in the circuit shown in
FIG. 1A
is “VSS−VTH”: VTH is the threshold voltage of the transistor QN
101
). As a result, the output signal OUT
101
changes to “L” level.
Note that the transistors QP
101
, QP
102
, QN
101
, and QN
102
are of enhancement type in order to prevent a leakage current from flowing through each transistor when the input signal IN
101
is at either “H” level or “L” level.
In the level-shifting circuit shown in
FIG. 1A
, to change the output signal OUT
101
from “L” level to “H” level as the input signal IN
101
changes from “L” level to “H” level, the drivability of the transistor QN
102
must be set higher than that of the transistor QP
102
. If the drivability ratio of these transistors is small, both the transistors QN
102
and QP
102
stay ON, so a punch-through current flows from the boosted potential VPP to the ground potential VSS. That is, the level-shifting circuit malfunctions.
Under these circumstances, the drivabilities of the transistors QN
101
and QN
102
are conventionally set much higher than those of the transistors QP
101
and QP
102
. However, a low power supply potential VCC decreases the current drivabilities of the transistors QN
101
and QN
102
. To suppress the decrease in current drivability, the channel widths of the transistors QN
101
and QN
102
must be large.
To raise the switching speed, an inverter I
102
for driving the transistor QN
102
and an inverter I
101
for driving the inverter I
102
and transistor QN
101
are large in size. However, this cannot avoid a long switching time Tr
2
from “L” level to “H” level and a long switching time Tf
2
from “H” level to “L” level shown in
FIG. 1B
, i.e., a low switching speed.
The switching speed varies more remarkably along with a decrease in power supply potential VCC. For example, the threshold voltage of a transistor varies due to manufacturing variations and the like. A low power supply potential VCC greatly influences the current amount flowing through the transistors QN
101
and QN
102
even with slight variations in threshold voltage. For this reason, the switching speed varies more remarkably along with a decrease in power supply potential VCC.
If the power supply potential VCC drops to values in the neighborhoods of the threshold voltages of the transistors QN
101
and QN
102
, the level-shifting circuit shown in
FIG. 1A
cannot operate.
In the conventional level-shifting circuit, the switching speed decreases with a decrease in power supply voltage.
Further, if the power supply voltage drops to about the threshold voltage, the conventional level-shifting circuit cannot operate.
BRIEF SUMMARY OF THE INVENTION
The present invention has been made in consideration of the above situation, and has as its object to provide a semiconductor integrated circuit device having a level-shifting circuit capable of suppressing a decrease in switching speed even if the power supply potential drops, and capable of operating even if the power supply voltage drops to about the threshold voltage.
To achieve the above object, according to the present invention, there is provided a semiconductor integrated circuit device comprising a first transistor of a first conductivity type having a source for receiving a first potential, a second transistor of the first conductivity type having a source for receiving the first potential, a gate connected to a drain of the first transistor, and a drain connected to a gate of the first transistor, and a third transistor of a second conductivity type having a drain connected to the drain of the first transistor, a gate for receiving a first signal, and a source for receiving a second signal.
In the semiconductor integrated circuit device having the above arrangement, the second signal is input to the source of the third transistor without fixing the source potential. Thus, the third transistor can be turned off by the logic level of the second signal input to the source, unlike the prior art in which the third transistor is turned off by the logic level of the first signal input to the gate. This arrangement allows operation of the semiconductor integrated circuit device even if the threshold voltage of the third transistor is set lower than in the prior art.
Assuming that a level for turning on the third transistor among the logic levels of the first signal is equal to that in the prior art, the threshold voltage of the third transistor can be decreased to increase the current amount flowing through the third transistor. Since the current amount flowing through the third transistor can be increased, deterioration of the drivability can be suppressed

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