Semiconductor integrated circuit device

Details Semiconductor integrated circuit device Semiconductor integrated circuit device

2001-05-02

2002-08-13

Smith, Matthew (Department: 2825)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C438S197000

Reexamination Certificate

active

06433438

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to a semiconductor integrated circuit device and to a fabrication process thereof, and more particularly, the invention relates to a technique which is effective when applied to a semiconductor integrated circuit device, which is fabricated by a process including a planarization step using the CMP (Chemical Mechanical Polishing) method.
To satisfy the continuing tendency to decrease the minimum processing size of a semiconductor integrated circuit device, in an exposure optical system, an increase in the performance of a stepper is required, which promotes a widening of the aperture size of a lens and a shortening of the exposure wave length. As a result, the focus depth of the exposure optical system decreases and even a slight unevenness on the surface to be processed becomes a problem. Therefore, the accurate planarization of the surface to be processed becomes an important technical objective for the device process. Furthermore, the above planarization does not aim at the easing of a stepped portion for the purpose of preventing a short cut of interconnections formed on the stepped portion, but is directed to a global planarization, in other words, a complete planarization.
As a surface planarization technique, there are a method of coating an SOG (Spin On Glass) film or a low-melting-point glass by melting it, a method of heat treatment through glass flow, a self planarization method adopting a surface reaction mechanism of CVD (Chemical Vapor Deposition) and the like. Owing to the surface conditions, to the heat treatment conditions being applied or to limitations in processing, in many cases, it is impossible to carry out complete planarization, that is, global planarization, using these methods. Therefore, the etchback and CMP processes are regarded as promising practical techniques which permit complete planarization.
As for the etchback process, the use of a photoresist as a sacrificial film, the use of an SOG film and the use of a self-planarization CVD film are known, but they are accompanied by such drawbacks as a complex procedure, a high cost and a lowering of the yield due to production of particles. The CMP process has, on the other hand, come to be regarded as an excellent process from an overall viewpoint, because, compared with the etchback process, it is more free from the above-described problems. Consequently, the CMP process is considered to be most promising as a practical technique for effecting complete planarization.
The CMP technique is described in, for example, Japanese Patent Application Laid-Open No. HEI 7-74175, U.S. Pat. No. 5,292,689 and “1996 Symposium on VLSI Technology Digest of Technical Papers, 158-159(1996)”.
SUMMARY OF THE INVENTION
During the investigation of a technique for the complete planarization of a device surface to which the CMP method is applied, which technique is not, however, a known process, the present inventors have recognized that there are the following drawbacks.
FIGS.
29
(
a
) to
29
(
d
) are each a cross-sectional view illustrating a planarization technique using the CMP method which the present inventors have investigated. For covering an interconnection with an insulating film and then planarizing the insulating film, an interconnection
102
is formed on an interlayer insulating film
101
(FIG.
29
(
a
)); a first insulating film
103
and a second insulating film
104
, such as SOG, are deposited to embed a concave portion thereof by the plasma CVD method or the like using TEOS (Tetraethoxysilane: (C
2
H
5
O)
4
Si) (FIG.
29
(
b
)); a third insulating film
105
is deposited by the plasma CVD method using TEOS (FIG.
29
(
c
)); and then the third insulating film
105
is polished by the CMP method for effecting planarization (FIG.
29
(
d
)).
At the present time, in the designing of a layout based on principles of functional design and logic design, the most important consideration concerning the pattern of the interconnection
102
has been based on whether the pattern follows the ordinary layout rule or not, and polishing properties in the CMP step have not been taken into particular consideration.
The interconnection pattern is therefore not uniform, being sparse in some places and dense in some places. In the drawing illustrating the technique under investigation (FIG.
29
(
d
)), it is seen that the interconnections
102
are dense in the portion A, while they are sparse in the other region. When CMP polishing is conducted under such a state, that is, a state where interconnections
102
are not disposed uniformly, being sparse in some places and dense in some places, the surface of the third insulating film
105
cannot be planarized completely. In a region where the interconnections
102
are dense, there appears a difference of 0.2 to 0.3 &mgr;m in height in the region A and a large undulation inevitably remains on the surface.
On the surface having such an undulation, the processing margin lowers in the subsequent photolithography step or etching step, and it becomes difficult to satisfy minute processing and heightening requirements of integration, which makes it impossible to bring about an improvement in the reliability of the semiconductor integrated circuit device and also an improvement in the yield. In addition, the existence of an undulation requires the optimization of the process conditions in order to carry out lithography and etching favorably in such a state, and an optimization of the CMP step also becomes necessary to suppress the undulation to a minimum. The time required for such optimization sometimes undesirably delays the starting time of the mass-production process.
In the region where the interconnections
102
are disposed sparsely, the recess between the interconnections
102
is not embedded sufficiently with the second insulating film
104
, and so the third insulating film
105
must be thicker in order to fill in such a recess completely, which consequently causes problems, such as an increase in the polishing amount of the third insulating film
105
and a rise in the step load in the CMP step, as well as an increase in the step load, such as a long deposition time, of the third insulating film
105
.
An object of the present invention is to completely planarize the surface of a member which has been polished by the CMP method.
Another object of the present invention is to provide a technique which can improve the processing margin in the photolithography and etching steps, thereby to achieve minute processing and an increased integration, while, at the same time, improving the reliability and yield of the semiconductor integrated circuit device.
A further object of the present invention is to facilitate the start of the process.
A still further object of the present invention is to reduce the amount of polishing of a member to be polished by the CMP method and to decrease the load and time of the polishing step, thereby improving the cost competitive advantage.
A still further object of the present invention is to provide a method of designing a member pattern which can be planarized completely by the CMP method.
A still further object of the present invention is to suppress an increase in the parasitic capacitance of an interconnection or the like which is caused by the measures to achieve complete planarization, thereby maintaining the performance of the semiconductor integrated circuit device.
The above-described and other objects, and novel features of the present invention will be more apparent from the following description and accompanying drawings.
Typical features of the invention disclosed by the present application will be described briefly.
(1) The semiconductor integrated circuit device according to the present invention comprises actual interconnections which are formed on a principal surface of a semiconductor substrate or an interlayer insulating film constituting a semiconductor integrated circuit element, and an insulating film containing a film which covers the actual interconnections and has been

Affiliated with

Also associated with

Rating

Semiconductor integrated circuit device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor integrated circuit device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2943925