Semiconductor integrated circuit device

Details Semiconductor integrated circuit device Semiconductor integrated circuit device

2001-05-03

2002-06-04

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Digital code to digital code converters

Parallel to serial

C341S100000

Reexamination Certificate

active

06400292

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device having a program element such as a fuse.
2. Description of Related Art
FIG. 18
is a schematic circuit diagram of a conventional semiconductor integrated circuit device having a fuse element. In
FIG. 18
, reference numeral
101
designates a fuse element group (FUSEG);
102
designates a fuse state detection circuit group (FDG) for detecting the ON/OFF state of fuse elements;
103
designates a random access memory or RAM;
1031
designates a main memory access array (MMCA);
1032
designates a redundancy memory cell array for columns (RMCAC); and
1033
designates a redundancy memory cell array for rows (RMCAR). Reference symbols F
0
-F
3
each denote a fuse element; and FD denotes a fuse state detection circuit.
Here, the fuse elements F
0
, F
1
, F
2
, and F
3
in the fuse state detection circuit group
101
can be cut or shorted according to information to be programmed by current, laser beam, voltage, and so on. Though only the four fuses are depicted in
FIG. 18
, a real semiconductor integrated circuit device is constructed by containing more than four fuses.
On the other hand, each fuse state detection circuit FD in the fuse state detection circuit group
102
detects the ON/OFF state of whether the corresponding fuse is cut or not, and then outputs “1” or “0” as a logic signal. The fuse state detection circuit group
102
outputs the information of a plurality of bits.
As to the RAM
103
, in
FIG. 18
, reference symbol A denotes an address terminal; WE denotes a write enable terminal; and DIO denotes a data input/output terminal, which may be replaced by a terminal provided with an data input terminal and a data output terminal discretely. In response to information output from the fuse state detection circuit group
102
, the RAM
103
can replace part of the main memory cell array
1031
with the corresponding part of the redundancy memory cell array for columns
1032
or the redundancy memory cell array for rows
1033
. Such a function is utilized for the correction or relief of a defective memory cell of the main memory cell array.
The redundancy memory cell array for columns
1032
is applied for the correction of a bit line fault and an in-cell fault, while the redundancy memory cell array for rows
1033
is applied for the correction of a word line fault and an in-cell fault.
Next,
FIG. 19
is another schematic circuit diagram of a conventional semiconductor integrated circuit device having a fuse element. In
FIG. 19
, reference numeral
104
designates an (Error Checking and Correcting) error correction circuit which detects an error in a data transmission of ECC code and corrects the corresponding error point. The ECC is explained as follows: In order to detect an error and further correct this, bits for error detection or correction based on a certain rule are added to original data. Note that the same other numerals above denote the same or corresponding parts.
The semiconductor integrated circuit device as shown in
FIG. 19
, in addition to the circuit configuration of
FIG. 18
, is further added the ECC error correction circuit
104
to the fuse section, thus improving the yield of the semiconductor integrated circuit device. In this example, three bits for checking of F
4
, F
5
and F
6
is added to four information bits of F
0
, F
1
, F
2
and F
3
. That error correction method is disclosed in JP-B-5/82000.
Further,
FIG. 20
is yet another schematic circuit diagram of a conventional semiconductor integrated circuit device, which disposes a plurality of RAMs having a fuse element as shown in
FIGS. 18 and 19
. In
FIG. 20
, reference numerals
101
-
1
to
101
-n (n: natural number) each designate a fuse element group;
102
-
1
to
102
-n each designate a fuse state detection circuit group;
103
-
1
to
103
-n each designate a RAM; and
105
designates a random logic circuit, which carries out a control and data input/output for the RAMs
103
-
1
to
103
-n.
For this reason, the circuit configuration of
FIG. 20
requires a plurality of circuit compositions corresponding to n out of the fuse element groups
101
-
1
to
101
-n, fuse state detection circuit groups
102
-
1
to
102
-n, RAMs
103
-
1
to
103
-n, and ECC error correction circuits
104
-
1
to
104
-n. Note that the ECC error correction circuits
104
-
1
to
104
-n are eliminated if not required.
FIGS. 21A and 21B
are examples of circuit diagrams illustrating CRC (Cyclic Redundancy Code) circuits which correspond to conventional error correction techniques.
FIG. 21A
illustrates a CRC generation circuit, and
FIG. 21B
illustrates a CRC correction circuit. In
FIGS. 21A and 21B
, reference symbols G
1
to G
3
, D
1
to D
3
, and S
0
to S
6
each denote a flip-flop (FF).
These examples correspond to the CRC circuits of a characteristic polynominal: G(x)=1+X+X
3
. The CRC generation circuit of
FIG. 21A
adds check bits of 3 bits to information bits of 4 bits, while the CRC correction circuit of
FIG. 21B
input a CRC of 7 bits and corrects an error of 1 bit and can correct the error of 1 bit at any position in the 7 bits. However, the error of 2 bits or more cannot be corrected.
Hereinafter, the operation of the aforementioned circuits will be described briefly.
(1) As to Generation Operation of CRC (Referring to FIG.
21
A):
(1-1) Reset the flip-flops G
1
, G
2
, and G
3
(reset means not depicted).
(1-2) In a state that the signal input of SELSIG terminal is SELSIG=1, a clock is provided for the flip-flops G
1
, G
2
, and G
3
while the information bits of 4 bits to SIG terminal is inputted in series. At this time, the information bits of 4 bits is transferred at SEG terminal as it stands, and simultaneously the data of the check bits is generated in the flip-flops G
1
, G
2
, and G
3
.
(1-3) In a state that the signal input of SELSIG terminal is SELSIG=0, the data of the flip-flops G
3
, G
2
, and G
1
are outputted to SOG terminal in series.
On the basis of the above operation, the CRC of 7 bits (4 bits+3 bits) is outputted from the SOG output terminal.
(2) As to Error Correction Operation of CRC (Referring to FIG.
21
B):
(2-1) Reset the D
1
, D
2
, and D
3
to “0” (reset means not depicted).
(2-2) clocks are supplied
0
for the flip-flops D
1
to D
3
and S
0
to S
6
while the CRC of 7 bits are inputted in series from SIC terminal. Here, at the moment time the CRC of 7 bits is stored in the flip-flops S
0
to S
6
, error detection results of the flip-flop S
0
to the bits are outputted from COR output (“1” is outputted when an error exists). Accordingly, in SOC terminal, error corrected data is outputted to the bit of the flip-flop S
0
.
In
FIGS. 9 and 11
, the fuses F
4
to F
6
and flip-flops S
4
to S
6
are assigned to the check bits, while the fuses F
0
to F
3
and flip-flops S
0
to S
3
are assigned to the information bits. However, it is possible to change such an assignment. For example, the following is considered: the fuses F
0
to F
2
and flip-flops S
0
to S
2
are assigned to the check bits, while the fuses F
3
to F
6
and flip-flops S
3
to S
6
are assigned. In this case, the circuit must be changed to construct a counter with the flip-flops S
3
to S
6
, but not depicted since it is inferred with ease.
(2-3) In a state that the signal input of SIC terminal is SIC=0, clocks are supplied for the flip-flops D
1
to D
3
. Thus, an error detection result corresponding to the bit of the flip-flop S
0
is outputted to the COR output (“1” is outputted when an error exists). Accordingly, in SOC terminal, error corrected data is outputted to the bit of the flip-flop S
0
.
(2-4) In a state that the signal input of SIC terminal is SIC=0, when clocks according to 6 cycles are supplied for the flip-flops D
1
to D
3
and S
0
to S
6
, error corrected data is outputted in series from SOC terminal with respect to the remaining 6 bits.
However, when only the information bits of 4 bits are req

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