Static information storage and retrieval – Addressing – Combined random and sequential addressing
Reexamination Certificate
2000-03-14
2002-01-29
Zarabian, Amir (Department: 2824)
Static information storage and retrieval
Addressing
Combined random and sequential addressing
C365S205000, C365S190000, C711S005000
Reexamination Certificate
active
06343046
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device. In particular, it relates to a semiconductor integrated circuit device wherein a main memory unit and an auxiliary memory unit are formed on the same semiconductor substrate and a data transfer circuit is provided between the main memory unit and the auxiliary memory unit.
2. Description of the Related Art
Large-capacity semiconductor devices which are comparatively slow and inexpensive are commonly employed as the main memory devices used in computer systems; common DRAMs, which meet these requirements, are widely employed in this way.
Furthermore, attempts have recently been made in computer systems to increase the speed of the DRAMs which comprise the main memory units in response to an increase in speed of the system (in particular, an increase in speed of the MPU); however, this is insufficient with respect to the increase in speed of the MPU, and most systems incorporate a high-speed memory between the MPU and the main memory unit as an auxiliary memory unit. These auxiliary memory units are commonly termed cache memories, and high speed SRAMs or ECLRAMs or the like are commonly employed as such cache memories.
Actually installed cache memories include those which are provided outside the MPU and those which are installed within the MPU; recently, semiconductor memory devices have attracted attention in which the DRAM which comprises the main memory unit and the cache memory are installed on the same semiconductor substrate. Conventional examples thereof include those disclosed in, for example, Japanese Patent Application, First Publication No. SHO 57-20983, Japanese Patent Application, First Publication No. SHO 60-7690, Japanese Patent Application, first publication No. SHO 62-38590, and Japanese Patent Application, First Publication No. HEI 1-146187. These preceding technology semiconductor memory devices have both a DRAM and cache memory installed, and have come to be termed by some cache DRAMs. Furthermore, they are also termed CDRAM. These have a structure in which data may be transferred in both directions between the SRAM which functions as the cache memory and the DRAM which functions as the main memory unit.
This preceding technology had problems, such as a delay in the data transfer operation during cache mishits, so that improved technology was proposed. The improved conventional technology was that described below. For example, in the technology disclosed in Japanese Patent Application, First Publication No. HEI 4-252486, Japanese Patent Application, First Publication No. HEI 4-318389, and Japanese Patent Application, First Publication No. HEI 5-2872, the characteristic feature was that a latch or a register function was provided in the bidirectional data transfer circuit which served to conduct data transfer between the DRAM and SRAM unit; this was capable of simultaneously conducting data transfer from the SRAM to the DRAM unit and from the DRAM unit to the SRAM unit, and enabled an increase in data transfer (copy back) speed during cache mishits.
This technology will be explained using as an example that disclosed in Japanese Patent Application, First Publication No. HEI 4-318389.
FIG. 17
shows, in schematic form, an example of the structure of an CDRAM memory array unit. In
FIG. 17
, the semiconductor memory devices contains a DRAM array
9201
which contains dynamic type memory cells, and an SRAM array
9202
which contains static type memory cells, and a bidirectional transfer gate circuit
9203
, which serves to conduct data transfer between the DRAM array
9201
and the SRAM array
9202
. Furthermore, each of the DRAM array
9201
and the SRAM array
9202
are provided with a corresponding row decoder and column decoder. The addresses assigned to the row decoder and column decoder of the DRAM and the row decoder and column decoder of the SRAM are independent of one another, and the structure is such that this assignment is conducted via differing address pin terminals.
FIGS. 18 and 19
show the details of the structure of the bidirectional transfer gate circuit
9203
. By means of the structure depicted, the data transfer from SBL to the GIO and the data transfer from the GIO to the SBL employ differing data transfer paths, and as a result of the function of the latch
9305
and amplifier
9306
, it is possible to execute these data transfers in an overlapping fashion.
In semiconductor integrated devices, among functions which relate to the entirety of the package, a decrease in power consumption and an increase in operational speed are commonly desired. In general, when the operating voltage is increased, it is possible to achieve an increase in operating speed; however, as a result, the power consumption tends to rise. When on the other hand, the operational voltage is set at a low level in order to achieve a reduction in power consumption, this entails a sacrifice of operating speed.
In CDRAMs employing the conventional technology described above, in order to achieve a reduction in power consumption, the operating voltage of the DRAM which serves as the main memory unit is set at a low level, while in contrast, the operating voltage of the SRAM which functions as a cache memory and forms the auxiliary memory unit is set at a high level to accommodate the requirement of an increase in speed.
The bidirectional transfer gate circuit depicted in
FIG. 17
is extremely important in order to conduct data transfer between the main memory unit and the auxiliary memory unit, which have differing operational power levels. The reason for this is that, in semiconductor memory circuit devices in which a cache memory such as that described above is installed, because the operating voltage of the main memory unit is low, there are cases in which a plurality of processes must be executed simultaneously, such as when data transfer is conducted in an overlapping manner as in the case of the CDRAM described above, and in such cases, the internal noise generated as a consequence of the operation of the circuitry reaches a high level and this tends to result in operational errors within the circuitry. In particular, in cases in which an DRAM which handles extremely weak data signals is employed as the chief memory unit, it is necessary to effectively suppress the internal noise generated. In this situation, problems are caused even when data transfer is conducted between the main memory unit and the auxiliary memory unit.
Furthermore, in recent years, an increase in operational speed has been required of semiconductor integrated circuit devices, as described above; however, if data transfer can not be efficiently conducted between a main memory unit and an auxiliary memory unit which have different operational voltages, it is impossible to obtain an increase in operating speed.
SUMMARY OF THE INVENTION
The present invention was created in light of the above circumstances; it has as an object thereof to provide a semiconductor integrated circuit device which is capable of efficiently conducting data transfer between a main memory unit and an auxiliary memory unit which operate at different operational voltages, and moreover, is capable of operating in a stable manner while effectively suppressing internal noise which is generated.
In order to solve the problem described above, a first semiconductor integrated circuit device of the present invention is provided with a main memory unit and an auxiliary memory unit which functions as a cache memory and has a structure in which bidirectional data transfer is possible via a data transfer bus line which is provided between the main memory unit and the auxiliary memory unit, and furthermore, this device is provided with a power source mechanism which supplies to the data transfer bus line, when data is not being transferred, a voltage which is lower than the power source voltage supplied to the main memory unit.
The device of the present invention may be provided with a sense amplifier circuit w
Nguyen Van-Thu
Young & Thompson
Zarabian Amir
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