Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2000-03-14
2002-01-01
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Interconnection arrangements
C365S230030, C365S149000, C365S051000
Reexamination Certificate
active
06335873
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor integrated circuit devices having plenty of external I/O terminals for inputting and outputting data, and particularly to semiconductor integrated circuit devices in which data transfer circuits are provided between main storages and auxiliary storages being formed on same semiconductor substrates.
This application is based on Patent Application No. Hei 11-69308 filed in Japan, the content of which is incorporated herein by reference.
2. Description of the Related Art
In general, computer systems use semiconductor devices of large capacities, in which processing speeds are relatively slow and costs in manufacture are relatively low, as main storage devices. To suite requirements of the main storage devices, the computer systems frequently use general-purpose DRAMs (i.e., dynamic random-access memories).
In the computer systems in these days, engineers develop DRAMs, which construct main storage portions, to increase processing speeds to cope with high-speed performance of the systems (particularly, high-speed performance of MPUs or microprocessing units). However, increasing the speeds of the DRAMs do not sufficiently catch up with the high-speed performance of the MPUs. To compensate gaps between speeds of the DRAMs and MPUs, the engineers design the computer systems to include high-speed memories between the main storages and MPUs as auxiliary storages. Those auxiliary storages are generally called “cache memories”, which correspond to high-speed SRAMs (static random-access memories), ECLRAM (where “ECL” stands for “Emitter-Coupled Logic”), etc.
In general, the cache memories are provided externally of the MPUs, or they are built in the MPUs. Recently, engineers pay attention to semiconductor storage devices, in which DRAMs constructing main storages and cache memories are formed on same semiconductor substrates. Related arts regarding the aforementioned semiconductor storage devices are disclosed by a variety of papers and documents, as follows:
Japanese Patent Application, First Publication No. Sho 57-20983 discloses an example of a memory chip, which is equipped with an internal port for connecting memory cells with a latch circuit to transfer data.
Japanese Patent Application, First Publication No. Sho 60-7690 discloses an example of a semiconductor memory, in which data of dynamic memory cells are transferred to static memory cells by transfer gates with respect to rows.
Japanese Patent Application, First Publication No. Sho 62-38590 discloses an example of a semiconductor memory device, in which data transfer is made between a DRAM and an SRAM with respect to rows.
Japanese Patent Application, First Publication No. Hei 1-146187 discloses an example of a semiconductor memory device incorporating a cache memory, in which data of memory cells are transferred to data registers by units of blocks by way of transfer gates, which are selected by a block decoder.
The semiconductor storage devices of the aforementioned related arts are sometimes called “cache DRAMs” because they contain DRAMs and cache memories. Or, they may be described in connection with “CD-RAMs”, for example. They are configured to enable bidirectional transfer data between SRAMs, functioning as cache memories, and DRAMs constructing main storages.
The aforementioned related arts suffer from drawbacks such as operational delays in data transfer due to cache mishit events, for example. So, engineers propose a variety of techniques regarding improvements to the semiconductor storage devices, as follows:
Japanese Patent Application, First Publication No. Hei 4-252486 discloses an example of a semiconductor memory device, in which data blocks are transferred from a DRAM array to an SRAM array as a cache memory.
Japanese Patent Application, First Publication No. Hei 4-318389 discloses an example of a data transfer device applied to a semiconductor storage device, in which data transfer is performed between a DRAM and an SRAM, wherein transfer data are rewritten as write data to allow access to the SRAM after completion of the data transfer to the DRAM to cope with a cache miswrite event.
Japanese Patent Application, First Publication No. Hei 5-2872 discloses an example of a semiconductor storage device, in which data transfer is performed between a DRAM and an SRAM by way of a bidirectional transfer gate circuit, wherein different paths are provided for the DRAM in writing and reading data respectively in a non-multiplex manner to allow data transfer from the DRAM to the SRAM at a high speed even in a cache-miss event.
The aforementioned techniques are characterized by incorporating bidirectional data transfer circuits, which are used to perform data transfer between DRAMs and SRAMs and which contain functions of latches and registers. So, each semiconductor storage device incorporating the aforementioned technique is designed such that first transfer of data being transferred from the SRAM to the DRAM can be performed simultaneously with second transfer of data being transferred from the DRAM to the SRAM. This enables data transfer (or copy-back) to be made faster in a cache mishit event.
However, the aforementioned techniques are disadvantageous in that an area of the bidirectional data transfer circuit is large enough to occupy an overall area of the semiconductor substrate. So, there is a limit in a number of the circuits being installed on the semiconductor substrate. As a result, there is a limit in a number of transfer bus lines being provided with respect to the semiconductor storage device. For this reason, a number of bits being transferred between a DRAM array and an SRAM array at once is limited to sixteen (bits). Generally speaking, a cache hit rate is reduced as a number of bits being transferred at once becomes small.
FIG. 46
shows a recent example of a memory system being equipped with multiple processing devices. Such a memory system of
FIG. 46
suffers from a drawback in which a cache hit rate is reduced upon receipt of access requests from the multiple processing devices. The multiple access requests given from the multiple processing devices (or memory masters) are frequently connected with address requests with regard to different sets (or rows). If a CD-RAM or ED-RAM (where “ED” stands for “Exchangeable Disk”) is used as a main memory (
9115
) shown in
FIG. 46
, the cache hit rate is reduced, so that the memory system as a whole is limited in high-speed performance. To cope with an increasing number of systems each having multiple processing devices (or memory masters) in these days, main memories should be designed to respond to multiple kinds of access requests rather than a single kind of memory access, which is conventionally made.
In addition to the aforementioned problems, engineers should consider other problems such as soft errors, which are caused to occur due to neutrons being introduced into very fine structures of memory cells in these days.
Conventionally, as a main course of occurrence of soft errors, scientists and engineers name alpha (&agr;) rays being produced by decays that occur on very small amounts of radioactive isotopes being contained in packages and wiring materials inside of semiconductor chips. As another cause, Dr. J. F. Ziegler names cosmic rays in 1979, which is discussed in a paper entitled “Effect of cosmic rays on computer memories” in Science, vol. 206, pp. 776-788, November 1979. However, scientists and engineers do not show interests on such a cause for a long time.
Recently, rapid developments of fine structures of memory cells press the scientists and engineers to observe modes regarding defectiveness of memory cells in which data of multiple bits are inverted due to soft errors, which are considered to be caused by cosmic rays. As a result, they show great interests in soft errors due to neutrons. A mechanism in occurrence of the soft errors due to neutrons is described as follows:
Cosmic rays collide with atoms of the atmosphere of the Earth to produce n
Fujii Takeo
Furuta Hiroshi
Hannai Seiichi
Kawaguchi Masaki
Matsui Yoshinori
Hoang Huan
NEC Corporation
Sughrue & Mion, PLLC
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