Semiconductor integrated circuit device

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371 161, 371 226, G01R 1512, G06F 1132

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active

049673874

ABSTRACT:
A microprocessor having a plurality of memories comprises an address selection means which supplies selectively, to the memories, the address signal generated by the address generation means provided in the microprocessor and the test address signal supplied from the external circuit. Thereby, the address of memories can be accessed directly from the external circuit for the test of memories. Moreover, the microprocessor is provided with the test bus through which the signal transmitted between the function blocks in the microprocessor is input or output from or to the external circuit. Accordingly, the function block can be tested easily.

REFERENCES:
patent: 3961251 (1976-06-01), Hurley et al.
patent: 3961254 (1976-06-01), Cavaliere et al.
patent: 4339819 (1982-07-01), Jacobson
patent: 4706186 (1987-11-01), Mogi et al.
patent: 4799004 (1989-01-01), Mori
"LSI Handbook", Issued on Nov. 30, 1988, by OHM CO., Ltd., p. 478. (Document Provided in Japanese with an English Translation Attached.).

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