Semiconductor integrated circuit device

Details Semiconductor integrated circuit device Semiconductor integrated circuit device

2000-06-15

2001-11-06

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S230060

Reexamination Certificate

active

06314044

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device, and principally to a technique effective for use in a RAM (Random Access Memory) mounted so as to mix with logic circuits.
With advances in semiconductor technology, a large scale integrated circuit is proceeding toward an approach or method for making combinations of large-scaled macros (cores) in a manner similar to the design of a printed circuit board by combinations of parts. A memory is essential to digital signal processing. Particularly since a dynamic RAM has a feature that large storage capacity is obtained, it plays an important role as for the above-described large scale integrated circuit.
The dynamic RAM is divided into a plurality of banks. Read or write operation is performed on each selected bank. Such a method of selecting a bank or a specific region or the like has been described in Japanese Patent Application Laid-Open Nos. Hei 9-245474, 2-83895, 4-313886 and 9-106684.
SUMMARY OF THE INVENTION
The inventors or the like of the present application has contemplated the standardization of a RAM core in consideration of the fact that when many kinds of RAM cores are prepared as the RAM placed or mounted in the above-described large scale integrated circuit according to individual requests, their development and management will result in trouble and complexity. They have thought of a novel operation control method which has taken into consideration ease of use as for a RAM mounted in a semiconductor integrated circuit device.
An object of this invention is to provide a semiconductor integrated circuit device equipped with a RAM provided in diverse configurations while its design and management are being simplified. Another object of this invention is to provide a semiconductor integrated circuit device which has improved ease of use as for a RAM incorporated therein. The above and other objects, and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
A summary of a typical one of the inventions disclosed in the present application will be described in brief as follows: A RAM mounted so as to mix with logic circuits has a configuration wherein one control circuit is commonly provided for a plurality of memory mats each including a memory array in which a plurality of memory cells are respectively placed at points where a plurality of word lines and a plurality of bit lines intersect, and an address selection circuit for performing selecting operations on the word lines and the bit lines. Further, the number of memory mats is determined according to the required storage capacity, arithmetic circuits for respectively performing +1 or −1 arithmetic operation are respectively provided in the memory mats and connected in cascade form and include a first-stage arithmetic circuit having an input terminal supplied with address-setting address signals formed as fixed or programmable, input signals supplied to the arithmetic circuits or signals outputted therefrom are defined as address signals assigned thereto, and each of comparators makes comparisons for coincidence between the address signals and address signals inputted upon memory access, whereby each memory mat activates an address selecting operation according to the coincidence signal.


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patent: 0741387 (1996-11-01), None
patent: 2-83895 (1990-03-01), None
patent: 4-313886 (1992-11-01), None
patent: 9-106684 (1997-04-01), None
patent: 9-245474 (1997-09-01), None
D. Wortzman, “Multiplexing Data Gates and I/O Orthogonally”, IBM Technical Disclosure Bulletin, vol. 27. No. 4B, Sept. 1, 1984, pp. 2651-2654.

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