Semiconductor integrated circuit device

Details Semiconductor integrated circuit device Semiconductor integrated circuit device

1998-02-12

2001-04-17

Chin, Stephen (Department: 2734)

Pulse or digital communications

Synchronizers

C375S355000, C375S377000, C327S141000, C327S142000, C327S147000, C327S153000

Reexamination Certificate

active

06219393

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
This invention relates to a semiconductor integrated circuit device comprising flip-flop for taking thereinto a reset signal in synchronism with a clock signal.
PRIOR ART
Generally, a semiconductor integrated circuit device
40
comprising a flip-flop for taking thereinto a reset signal in synchronism with a clock signal includes, as shown in
FIG. 7
, a clock generating circuit
2
and an operating circuit
6
. The clock generating circuit
2
generates, on the basis of a clock signal f
ex
sent from the outside, a clock signal f
i
having frequency different from frequency of this clock signal f
ex
. The operating circuit
6
is a circuit including a portion operative in synchronism with the clock signal f
i
.
It is now assumed that the clock generating circuit
2
and the operating circuit
6
respectively include flip-flops. Particularly, such a flip-flop for which application of clock pulse is required at the time of reset of the operating circuit is necessarily included in the operating circuit
6
, and that clock is assumed to be delivered from the clock generating circuit
2
. Such a flip-flop takes thereinto reset signal for carrying out clear operation or preset operation in synchronism with clock. On the other hand, whether or not the flip-flop included in the clock generating circuit
2
requires application of clock pulse in the reset operation is arbitrary.
Hereinafter, the clear operation and the preset operation of the flip-flop carried out at the time of reset are assumed to be collectively called “reset operation”. In addition, such a flip-flop to take thereinto reset signal in synchronism with clock is assumed to be called “Synchronous reset type flip-flop”.
The conventional semiconductor integrated circuit device
40
constituted as described above is used in a manner as described below. For example, in the case where because frequency of the clock signal f
ex
is too high, the operating circuit
6
is unable to become operative in synchronism with the clock signal f
ex
from a viewpoint of performance, the device
40
is used in such a manner that the clock signal f
ex
is frequency-divided by the clock generating circuit
2
to generate a clock signal f
i
of low frequency thereafter to allow the operating circuit
6
to be operative by using this clock signal f
i
. In this case, the clock generating circuit
2
is realized as a frequency-dividing circuit. In addition, the device
40
is used also in such a manner to generate, as clock signal f
i
, clock in which the clock signal f
ex
is caused to be high speed clock to allow the operating circuit
6
to be operative by using this clock signal f
i
. In this case, the clock generating circuit
2
is realized as a multiplication circuit.
Let now consider the case where reset signal is inputted from the outside to the semiconductor integrated circuit device
40
shown in FIG.
7
.
A semiconductor integrated circuit device
50
in the case where reset signal S
R
is applied to the semiconductor integrated circuit device
40
of
FIG. 7
is shown in FIG.
8
. The reset signal S
R
is delivered to both clock generating circuit
2
and operating circuit
6
in order to initialize flip-flops included in the clock generating circuit
2
and the operating circuit
6
.
However, in the semiconductor integrated circuit device
50
constituted as shown in
FIG. 8
, it is indicated in a manner as described below that the reset operation is not correctly carried out in the operating circuit
6
. Since the clock generating circuit
2
is initialized for a time period during which the reset signal S
R
is in enable state, no clock pulse is outputted to the operating circuit
6
. For this reason, the synchronous reset type flip-flop within the operating circuit
6
cannot take reset signal S
R
thereinto. After the reset signal S
R
is released and the clock generating circuit
2
thus begins to operate, clock pulse f
i
is outputted to the operating circuit
6
. For this reason, the operating circuit
6
cannot take thereinto reset signal by clock signal f
i
. Thus, reset operation is not carried out in connection with the operating circuit
6
. Namely, in order to reset the synchronous reset type flip-flop within the operating circuit
6
, it is necessary that both reset signal and clock for taking it thereinto after undergone synchronization are delivered to the operating circuit
6
. However, in the case of the circuit configuration of
FIG. 8
, since clock signal f
i
is not generated for a time period during which reset signal is generated, the reset operation is not carried out.
SUMMARY OF THE INVENTION
This invention has been made in view of the above-mentioned circumstances, and its object is to provide a semiconductor integrated circuit device capable of carrying out reliable reset operation.
A semiconductor integrated circuit device according to this invention comprises a first circuit which is reset on the basis of a reset signal to generate a clock signal, a delay circuit responsive to the reset signal to output a delayed reset signal, and a second circuit including a flip-flop operative in synchronism with the clock signal thus generated to take thereinto the delayed reset signal in synchronism with the generated clock signal.
In this case, the first circuit may be a frequency-dividing circuit for frequency-dividing an external clock signal delivered from the outside to thereby generate the clock signal.
Moreover, the first circuit may be a multiplication circuit for carrying out multiplication of an external clock signal delivered from the outside to thereby generate the clock signal.
Further, the first circuit may be a PLL circuit for extracting the clock signal from input data delivered from the outside.
Further, a semiconductor integrated circuit device of this invention may be constituted as a communication control unit for carrying out control of the physical layer in the hierarchical protocol of communication, wherein the second circuit is a data processing unit for implementing a predetermined processing to the input data in synchronism with a clock signal outputted from the PLL circuit to deliver the data thus processed to a control unit of high order protocol hierarchy.
Further, a semiconductor integrated circuit device of this invention comprises a communication control unit including a frequency-dividing element (frequency divider) which is reset by a reset signal to carry out frequency division of an external clock signal sent from the outside so that its frequency is changed into 1
value, a serial/parallel converting circuit which is reset by the reset signal and is operative to convert, on the basis of the external clock signal and a frequency-divided clock signal which is output of the frequency divider, serial received data sent in synchronism with the external clock signal into n bit parallel data, a delay circuit adapted to receive the reset signal to output a delayed reset signal, and a data processing circuit including a flip/flop for taking thereinto the delayed reset signal in synchronism with the frequency-divided clock signal to implement a predetermined processing to the n bit parallel data in synchronism with the frequency-divided clock signal to deliver it to a control unit of high order protocol hierarchy.
Further, the delay circuit may be comprised of a RC integrating circuit or an inverter chain.
In addition, the delay circuit may be comprised of a shift register operative in synchronism with a clock signal.


REFERENCES:
patent: 4450572 (1984-05-01), Stewart et al.
patent: 5122694 (1992-06-01), Bradford et al.
patent: 5297261 (1994-03-01), Kuranaga
patent: 5367543 (1994-11-01), Uomoto
patent: 5418816 (1995-05-01), Yamamoto
patent: 5510740 (1996-04-01), Farrell et al.
patent: 5825706 (1998-10-01), Snowden et al.
patent: 5886582 (1999-03-01), Stansell

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