Semiconductor integrated circuit device

Details Semiconductor integrated circuit device Semiconductor integrated circuit device

1999-10-29

2001-08-07

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S159000, C327S295000

Reexamination Certificate

active

06271697

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor integrated circuit devices, and more particularly, to a semiconductor integrated circuit device capable of supplying internal clock signals in various timings to internal circuit blocks and input/output latch circuits which operate synchronously with internal clock signals.
2. Description of the Background Art
In the field of semiconductor integrated circuit devices, with the advance of large scale integration and high speed operation of circuits, skews of clock signals are no longer ignorable. As the number of pins increases in response to such large scale integration of circuits, the magnitude of simultaneous switching noises poses a serious problem.
FIG. 21
is a block diagram showing an example of a conventional semiconductor integrated circuit device. Referring to
FIG. 21
, the LSI includes on a semiconductor substrate
100
, a driver transistor
101
, input buffer circuits
31
,
32
, and
33
, input latch circuits
41
,
42
and
43
, internal circuit blocks
21
,
22
and
23
, output latch circuits
51
,
52
and
53
, and output buffer circuits
61
,
62
and
63
.
First internal circuit block
21
receives as an input an externally applied first input data signal I
1
through first input buffer circuit
31
and first input latch circuit
41
. A first output data signal O
1
is output externally from the LSI from first internal circuit block
21
through first output latch circuit
51
and first output buffer circuit
61
.
Similarly, second internal circuit block
22
receives an external second input data signal I
2
through second input buffer circuit
32
and second input latch circuit
42
. A second output data signal O
2
is output externally from the LSI from second internal circuit block
22
through second output latch circuit
52
and second output buffer circuit
62
.
Similarly, third internal circuit block
23
receives as an input an externally applied third input data signal I
3
through third input buffer circuit
33
and third input latch circuit
43
. A third output data signal O
3
is output externally from the LSI from third internal circuit block
23
through third output latch circuit
53
and third output buffer circuit
63
.
Driver transistor
101
receives an external clock signal CLK which is externally applied to the LSI. Driver transistor
101
provides a single internal clock signal to first to third input latch circuits
41
to
43
, first to third internal circuit blocks
21
to
23
, and first to third output latch circuits
51
to
53
.
Now, operation of the LSI in
FIG. 21
will be described. Driver transistor
101
responds to external clock signal CLK and outputs a single internal clock signal simultaneously to first to third input latch circuits
41
to
43
, first to third internal circuit blocks
21
to
23
, and first to third output latch circuits
51
to
53
.
First to third input latch circuits
41
to
43
, first to third internal circuit blocks
21
to
23
, and first to third output latch circuits
51
to
53
operate in synchronization with the provided internal clock signal.
The operation will be described by way of illustrating the signal transmission path from first input buffer circuit
31
to first output buffer circuit
61
. First input data signal I
1
is applied to first input latch circuit
41
through first input buffer circuit
31
. First input latch circuit
41
performs a prescribed latch operation in synchronization with the applied internal clock signal, and applies the applied first input data signal I
1
to first internal circuit block
21
.
First internal circuit block
21
performs a prescribed signal processing to first input data signal I
1
in synchronization with the applied internal clock signal, and applies first output data signal O
1
to first output latch circuit
51
as a result. First output latch circuit
51
performs a prescribed latch operation in synchronization with the applied internal clock signal, and applies the applied first output data signal O
1
to first output buffer circuit
61
as a result. First output data signal O
1
is output externally from the LSI through first output buffer circuit
61
.
The operation of each element in the signal transmission path from second input buffer circuit
32
to second output buffer circuit
62
and the operation of each element in the signal transmission path from third input buffer circuit
33
to third output buffer circuit
63
are conducted similar to the operation of each element in the signal transmission path from first input buffer circuit
31
to first output buffer circuit
61
described above.
Such a conventional semiconductor integrated circuit device is encountered with the following problems for its configuration.
Firstly, difference in distances from driver transistor
101
to respective internal circuit blocks generates a clock skew for an internal clock signal between the internal circuit blocks, which results in erroneous operations when the LSI operates at a high speed.
Secondly, since all output data signals are outputted simultaneously in order that each output circuit can operate synchronously with a single internal clock signal, simultaneous switching noises are generated. The simultaneous switching noise is caused by currents which are passed through semiconductor substrate
100
in response to simultaneous switching operations of a plurality of output buffer circuits.
Thirdly, in a system for transmitting/receiving data signals between a plurality of LSIs, if a signal is delayed to different degrees between LSIs and yet the LSIs operate in the same operation timing, each LSI cannot appropriately receive a data signal output from another LSI for the delay of the data signal. In order to solve such a problem, input/output timings for data signals to/from LSIs must be different. In a conventional LSI, however, the operation timing of an input latch circuit and the operation timing of an output latch circuit are fixed. Changing input/output timings for data signals after LSIs are mounted onto the board requires troublesome operation of changing the phases of internal clock signals to be produced in the LSIs.
Finally, since in a conventional LSI input latch circuits have the same operation timing, if data signals are delayed differently for every signal line connected to each input latch circuit after the LSIs are mounted on the board, delay elements must be inserted in the signal lines in order to match the phases of data signals to be inputted to the input latch circuits. Similarly, if data signals are delayed differently for every signal line connected to each output latch circuit, a delay element must be inserted in each signal line in order to make the phases of output data signals in phase in an LSI to which that data signals are destined. Such insertion of delay elements in signal lines expands the mounting area of the circuit.
An invention related to a solution to clock skews between a plurality of LSIs for clock signals applied to the LSIs is disclosed, for example, in Japanese Patent Laying-Open No. 1-261018. The invention disclosed in the document includes within the LSI a delay signal generation circuit for generating a plurality of delay signals by delaying a clock input signal by small amounts, and a select circuit for selectively outputting a necessary delay signal from said plurality of delay signals. According to the document, the delay signal generation circuit and the select circuit adjust clock skews between a plurality of LSIs operating synchronously with a clock input signal.
As an invention directed to a solution to interphase skews in internal clock signals of a plurality of phases generated based on an external clock signal is disclosed, for example, in Japanese Patent Laying-Open No. 2-194721. The invention disclosed in the document includes a frequency dividing circuit for frequency-dividing an external clock signal and a differential circuit receiving the output signal of the frequency

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