Semiconductor integrated circuit device

Details Semiconductor integrated circuit device Semiconductor integrated circuit device

1999-09-23

2001-01-30

Zweizig, Jeffrey (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S291000

Reexamination Certificate

active

06181174

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor integrated circuit devices, and more particularly, to a semiconductor integrated circuit device equipped with a delayed locked loop (DLL).
Recently, semiconductor integrated circuit devices have been advanced to operate at a high speed and have a high integration density. Further, it has been required that a phase-synchronized clock signal is supplied to given circuits in the semiconductor integrated circuit devices. More particularly, a synchronous dynamic random access memory (SDRAM) is designed to be equipped with a DLL circuit, which supplies a signal synchronized in phase with an external clock signal to a plurality of output buffer circuits. The DLL circuit is required to have a higher precision in order to handle a higher frequency.
2. Description of the Related Art
FIG. 1
is a block diagram of a conventional DLL circuit. An external clock signal supplied to a clock input pad
150
from the outside of the circuit passes through an input circuit
152
and is supplied, as a real clock, to a delay circuit
154
and a frequency divider
156
. The frequency divider
156
frequency-divides the external clock signal at a frequency-dividing ratio of 2/8, and outputs a dummy clock Z and a reference clock X. The dummy clock Z is at a high level H during a period equal to two cycles of the external clock signal and is at a low level L during a period equal to six cycles thereof. The reference clock X is the inverted version of the dummy clock Z. That is, the reference clock X is at the low level L during the period equal to two cycles of the external clock signal, and is at the high level H during the period equal to six cycles thereof.
The reference clock X is supplied to a phase comparator
158
, while the dummy clock Z passes through a dummy delay circuit
160
and a dummy circuit
162
, and is then supplied to the phase comparator
158
. The dummy circuit
162
has the same circuit configurations as those of the input circuit
152
and an output circuit
168
. The phase comparator
158
compares the phase of the delayed dummy clock Z with the phase of the reference clock X and results in a phase difference signal, which is supplied to the delay control circuit
164
. The delay control circuit
164
controls, on the basis of the phase difference signal, a delay amount of the dummy delay circuit
160
so that the phase difference becomes zero. Thus, the delay amount of the dummy delay circuit
160
is controlled so that the rising edge of the dummy clock Z coincides with the rising edge of the reference clock X, that is, the delayed dummy clock Z lags behind the reference clock X by a delay of time equal to k cycles (k=2 in the case being concerned) of the external clock signal.
The delay circuit
154
supplied with the real clock has the same configuration as the dummy delay circuit
160
, and is set to the same delay amount as that of the dummy delay circuit
160
by the delay control circuit
164
. The real clock delayed by the delay circuit
154
is supplied to the output circuit
168
. The output circuit
168
buffers data on a data bus in synchronism with the real clock, and outputs buffered data via a data output pad
170
.
The dummy circuit
168
has the same configurations as those of the input circuit
152
and the output circuit
168
. Thus, the data output by the data output pad
170
is in phase with the external clock signal applied to the clock input pad
150
in the state in which the delayed dummy clock Z lags behind the reference clock X by the delay of time equal to k cycles of the external clock signal.
The conventional circuit shown in
FIG. 1
employs the frequency divider
156
which has a fixed frequency dividing ratio. In case where there is a small variable range of the frequency of the external clock signal, the circuit shown in
FIG. 1
will operate properly. In contrast, if the external clock signal changes over a wide frequency range, an underflow will occur when the frequency of the external clock signal becomes high. The underflow is defined so that the delay control circuit
164
continues to generate the signal which further reduces the delay amount nevertheless the delay circuits
154
and
160
respectively set the minimum delay amounts. In this case, the phase difference signal generated by the phase comparator
158
does not become zero, and thus the on-lock state cannot be obtained.
It is conceivable to increase the frequency dividing ratio of the frequency divider
156
and delay the rising edge of the reference clock X. However, in the above case, a situation in which the frequency of the external clock signal becomes low cannot be processed unless the delay circuits
154
and
160
are modified to have an increased number of delay stages in accordance with the delayed rising edge of the reference clock X. This increases the chip area. Further, the DLL circuit becomes likely to be affected by power system noise resulting from a variation in the power supply voltage because the above noise results from an accumulation of fine variations in the delay times in the respective delay stages.
SUMMARY OF THE INVENTION
It is a general object of the present invention to provide a semiconductor integrated circuit device in which the above disadvantages are eliminated.
A more specific object of the present invention is to provide a semiconductor integrated circuit device which does not cause an underflow and an overflow of a DLL circuit even if the frequency of the external clock becomes high and low, respectively and which needs no increase of the chip area and is hardly likely to be affected by power system noise.
The above objects of the present invention are achieved by a semiconductor integrated circuit device comprising a delayed locked loop circuit, which comprises: a frequency divider which frequency-divides an input clock at a frequency dividing ratio which is varied depending on a frequency of the input clock and thus results in a dummy clock and a reference clock; a delay system including a variable delay circuit which delays the dummy clock; and a control circuit which controls a delay amount of the variable delay circuit so that a phase of a delayed dummy clock from the delay system and the reference clock becomes zero.
The above objects of the present invention are also achieved by a semiconductor integrated circuit device comprising a 1/2 frequency divider which frequency-divides an input clock at a frequency dividing ratio of 1/2; a selector circuit which selects one of the input clock and a frequency-divided clock from the 1/2 frequency divider in accordance with a frequency of the input clock; and a delayed locked loop circuit including: a frequency divider which frequency-divides a selected clock from the selector circuit and produces a dummy clock and a reference clock; a delay system including a variable delay circuit which delays the dummy clock; a control circuit which controls a delay amount of the variable delay circuit so that a phase of a delayed dummy clock from the delay system and the reference clock becomes zero.


REFERENCES:
patent: 5929711 (1999-07-01), Ito
patent: 6066968 (2000-05-01), Yang

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