Semiconductor integrated circuit device

Static information storage and retrieval – Magnetic bubbles – Guide structure

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357 40, 357 45, 36523003, H01L 2702, H01L 2904

Patent

active

049909924

ABSTRACT:
A memory array is divided into a plurality of circuit blocks which each include wirings composed of electrically conductive polycrystalline silicon layers and circuit elements that will be operated by signals supplied via the wirings. Each circuit block is served with a signal via an aluminum layer. The signal supplied to the circuit block is transmitted to the circuit elements via an internal wiring. If the aluminum layer is broken the circuit block formed on the remote side beyond the broken portion fail to work properly. Therefore, breakage of the aluminum layer can be easily detected. Further, since signals are supplied to the circuit blocks via an aluminum layer, the memory array operates at increased speeds.

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patent: 4223333 (1980-09-01), Masuoka
patent: 4739497 (1988-09-01), Itoh et al.
M. Yoshimoto et al., "A 64kb Full CMOS RAM with Divided Word Line Structure", ISSCC 83, (Feb. 1983), pp. 58-59.

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