Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular signal path connections
Reexamination Certificate
1999-06-21
2001-04-24
Williams, Alexander O. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
With particular signal path connections
C257S203000, C257S207000, C257S499000, C257S784000, C257S202000
Reexamination Certificate
active
06222213
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the arrangement and structure of the input/output cells in a semiconductor device, particularly, in a semiconductor integrated circuit device.
2. Description of the Prior Art
FIG. 7
is a schematic view of a conventional semiconductor integrated circuit device. This semiconductor integrated circuit device has an internal logic circuit area
31
and two input/output cell groups
10
and
20
on a semiconductor substrate (not shown). The internal logic circuit area
31
is designed so as to have an arbitrary function. Signal wiring is provided between the two input/output cell groups
10
and
20
and the internal logic circuit area
31
or between the input/output cells of the input/output cell group
10
and the input/output cells of the input/output cell group
20
so that signal transfer is performed between the internal logic circuit area
31
and an external device (not shown) through the two input/output cell groups
10
and
20
.
The two input/output cell groups
10
and
20
comprise a plurality of input/output cells
11
and
21
, respectively. The input/output cells
11
and
21
are each arranged in a square loop so that the square internal logic circuit area
31
is surrounded by two loops.
The inside input/output cell group
10
comprises a multiplicity of input/output cells
11
and four corner cells
11
A comprising blank cells. The cells are arranged in a square loop on the semiconductor substrate so as to surround the square internal logic circuit area
31
situated substantially in the center of the semiconductor substrate. The outside input/output cell group
20
comprises a multiplicity of input/output cells
21
and four corner cells
21
A comprising blank cells. The cells are arranged in a square loop so as to surround the inside input/output cell group
10
.
A space
41
for providing wiring between the internal logic circuit area
31
and the outside input/output cell group
20
is provided between the inside input/output cell group
10
and the outside input/output cell group
20
. A space for providing wiring is also provided between the internal logic circuit area
31
and the inside input/output cell group
10
.
The input/output cells
11
of the inside input/output cell group
10
each have a high potential side guard band
12
, a low potential side guard band
13
and a bonding pad
14
. The high potential side guard band
12
is disposed on the side closer to the internal logic circuit area
31
. The low potential side guard band
13
is disposed outside the high potential side guard band
12
. The bonding pad
14
is disposed outside the low potential side guard band
13
. The high potential side guard band
12
is supplied with a high potential supply voltage V
DD
, whereas the low potential side guard band
13
is supplied with a low potential supply voltage V
SS
. The bonding pad
14
is connected to an external device to perform signal transfer with the external device.
The input/output cells
21
of the outside input/output cell group
20
each have a high potential side guard band
22
, a low potential side guard band
23
and a bonding pad
24
. The high potential side guard band
22
is disposed on the side closer to the internal logic circuit area
31
. The low potential side guard band
23
is disposed outside the high potential side guard band
22
. The bonding pad
24
is disposed outside the low potential side guard band
23
. The high potential side guard band
22
is supplied with the high potential supply voltage V
DD
, whereas the low potential side guard band
23
is supplied with the low potential supply voltage V
SS
. The bonding pad
24
is connected to an external device to perform signal transfer with the external device.
The corner cells
11
A have no guard bands. The corner cells
21
A each have a low potential side guard band
23
A electrically connected to the low potential side guard band
23
.
On the semiconductor substrate, wiring
51
as, for example, signal lines is provided. The wiring
51
made of a metal such as aluminum or copper electrically connects the internal logic circuit area
31
and the outside input/output cells
21
.
The input/output cells
11
and
21
are incorporated in the semiconductor integrated circuit device in order to perform signal transfer with an external device. The input/output cells
11
and
21
include not only input/output elements but also elements for protecting the semiconductor integrated circuit device from externally applied high voltages such as noises and bonding pads
14
and
24
for performing signal transfer with an external device.
FIG. 8
shows an example of an equivalent circuit of the input/output cells
11
. The input/output cells
11
each comprise, as shown in
FIG. 8
, a P-channel transistor
201
which is a P-channel input element, an N-channel transistor
202
which is an N-channel input element, a P-channel transistor
203
which is a P-channel output element, an N-channel transistor
204
which is an N-channel output element, a P-channel transistor
205
which is a P-channel protecting element, and an N-channel transistor
206
which is an N-channel protecting element.
The source of the P-channel transistor
201
is connected to the high potential supply voltage V
DD
. The source of the N-channel transistor
202
is connected to the low potential supply voltage V
SS
. The gate of the P-channel transistor
201
and the gate of the N-channel transistor
202
are joined and connected to the bonding pad
14
. The drain of the P-channel transistor
201
and the drain of the N-channel transistor
202
are joined and connected to the internal logic circuit area
31
.
The source of the P-channel transistor
203
is connected to the high potential supply voltage V
DD
. The source of the N-channel transistor
204
is connected to the low potential supply voltage V
SS
. The drain of the P-channel transistor
203
and the drain of the N-channel transistor
204
are joined and connected to the bonding pad
14
. The gate of the P-channel transistor
203
and the gate of the N-channel transistor
204
are joined and connected to the internal logic circuit area
31
.
The source and the gate of the P-channel transistor
205
are joined and connected to the high potential supply voltage V
DD
. The source and the gate of the N-channel transistor
206
are joined and connected to the low potential supply voltage V
SS
. The drain of the P-channel transistor
205
and the drain of the N-channel transistor
206
are joined and connected to the bonding pad
14
.
The input/output cells
21
have the same circuit structure as the input/output cells
11
.
Because of this circuit structure, the guard bands
12
,
13
,
22
and
23
are normally formed in the input/output cells
11
and
21
, and by the guard bands
12
,
13
,
22
and
23
, the input/output cells
11
and
21
are protected. By arranging the input/output cells
11
and
21
in loops, the guard bands
12
,
13
,
22
and
23
form rings surrounding the internal logical circuit area
31
, whereby the internal logic circuit area
31
is protected. The rings formed by the guard bands
12
,
13
,
22
and
23
are called guard rings.
The elements for protecting the semiconductor integrated circuit device from externally applied high voltages are provided for the following purpose: Since external signals are directly supplied to the semiconductor integrated circuit device through the bonding pads
14
and
24
, in order to protect the semiconductor integrated circuit device, an element is provided for causing an overcurrent to flow toward the high potential side when a high voltage is applied. In this case, toward the high potential side, the overcurrent is caused to flow from the drain of the P-channel transistor
205
which is a protecting element. Toward the low potential side, the overcurrent is caused to flow from the drain of the N-channel transistor
206
which is a protecting element.
By surrounding the portions where the overcurrent flo
Matsushita Electric - Industrial Co., Ltd.
Stevens Davis Miller & Mosher LLP
Williams Alexander O.
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