Patent
1985-12-11
1989-08-29
Larkins, William D.
357 42, 357 51, H01L 2710
Patent
active
048622419
ABSTRACT:
The inventive semiconductor integrated circuit device comprises a plurality of regularly disposed elementary units, each including a P channel MOS FET element paired with and an N channel MOS FET element. Desired ones of the elementary units each comprise a MOS field effect transistor having an ordinary form of a source-drain region formed by a diffusion region, while the remaining elementary units each have a diffusion region selectively connected to serve as a resistive element. Consequently, a desired circuit can be implemented without a resistive element being formed on each elementary unit.
REFERENCES:
patent: 4516312 (1985-05-01), Tomita
patent: 4549131 (1985-10-01), Kusazaki
Ashida Yasuhiro
Yokota Shigeki
Larkins William D.
Sanyo Electric Co,. Ltd.
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