Static information storage and retrieval – Interconnection arrangements
Patent
1987-04-09
1988-12-13
Popek, Joseph A.
Static information storage and retrieval
Interconnection arrangements
365 51, G11C 506
Patent
active
047916095
ABSTRACT:
A semiconductor integrated circuit device comprising a plurality of rows of logic cells, the rows of logic cells being spaced apart from each other to define channel areas therebetween, the logic cells being arranged to form a plurality of function blocks each having a predetermined logic function, and at least one wiring layer overlying the rows of logic cells and the channel areas, the wiring layer comprising a plurality of inter-cell wiring areas extending along the rows of logic cells and including interconnects between desired ones of the logic cells and inter-block wiring areas extending along the channel areas and including interconnects between desired ones of the function blocks. Each of the inter-cell wiring areas comprises wiring sections respectively associated with the function blocks and mostly consisting of wiring sections having widths within a predetermined range.
REFERENCES:
patent: 4525809 (1985-06-01), Chiba et al.
NEC Corporation
Popek Joseph A.
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