Patent
1984-09-28
1987-09-22
James, Andrew J.
357 231, 357 41, H01L 2702
Patent
active
046958665
ABSTRACT:
An improved layout configuration of an MOS transistor circuit is disclosed, which includes a plurality of series-connected insulated gate field effect transistors with a single common gate electrode. The plurality of transistors have their source and drain regions and channel regions positioned in an active region of U-shape or zig-zag shape in plane configuration delimited in a semiconductor substrate. On the other hand, the common gate electrode for all the transistors is formed of a single conducting layer extending in one direction or a single conducting layer having a component extending in one direction and a component extending in the direction at right angles to this one direction. According to such a layout configuration, the mentioned transistor circuit can be provided at a high integration density. This layout can be applied to a C-MOS inverter having a desired high value of an ON resistance which consists of a plurality of p-channel type unit transistors connected in series with one another and a plurality of n-channel type unit transistors connected in series with one another.
James Andrew J.
NEC Corporation
Prenty Mark
LandOfFree
Semiconductor integrated circuit device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor integrated circuit device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2061971