Patent
1981-10-15
1984-08-21
Edlow, Martin H.
357 54, 357 65, 357 69, H01L 2348, H01L 2944, H01L 2934, H01L 2952
Patent
active
044673450
ABSTRACT:
A semiconductor integrated circuit device is disclosed in which insulation faults occurring above the ground or power supply wiring are eliminated. In one embodiment of the invention, the ground or power supply wirings are divided into two or more substantially parallel wiring sections, which eliminates the surface upon which large grain size phosphorus silicate glass may form. In a second embodiment of the invention, the ground or power supply wirings are divided into two or more substantially parallel wiring sections in the vicinity of the exposed region of a bonding pad.
REFERENCES:
patent: 3620837 (1971-11-01), Leff et al.
patent: 3632433 (1972-01-01), Tokuyama et al.
patent: 3822467 (1974-07-01), Symersky
patent: 4109275 (1978-08-01), Sarkary
patent: 4223337 (1980-09-01), Kojima et al.
Edlow Martin H.
Jackson Jerome
Nippon Electric Co. Ltd.
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