Semiconductor integrated circuit design system,...

Details Semiconductor integrated circuit design system,... Semiconductor integrated circuit design system,...

2011-05-24

2011-05-24

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Physical design processing

C716S106000, C716S111000, C716S053000, C716S118000, C716S126000

Reexamination Certificate

active

07949982

ABSTRACT:
A semiconductor integrated circuit design method has extracting connection-permitted patterns which are permitted to connect to each other in a layout pattern, disconnection-permitted patterns which exercise no effect on a circuit operation even when disconnected in the layout pattern, and a multicut via which suffices when connection is made to at least one via thereof in the layout pattern, by using a net list and a cell library; conducting LRC (Lithography Rule Check) processing on the layout pattern to which a correction pattern resulting from OPC (Optical Proximity Correction) processing is added, and detecting an error part; and judging the error part either as a false error when the error part is included in the connection-permitted patterns, the disconnection-permitted patterns, or the multicut via extracted, or as a true error when the error part is not included in the connection-permitted patterns, the disconnection-permitted patterns, or the multicut via extracted, and making a pattern correction to the error part when the error part is judged as the true error.

REFERENCES:
patent: 2006/0271907 (2006-11-01), Izuha et al.
patent: 2007/0101307 (2007-05-01), Ueda

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