Semiconductor integrated circuit, delay-locked loop having...

Details Semiconductor integrated circuit, delay-locked loop having... Semiconductor integrated circuit, delay-locked loop having...

1998-07-02

2001-10-30

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S281000, C331S057000

Reexamination Certificate

active

06310505

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and, more particularly, to a semiconductor integrated circuit including a variable delay circuit, and to a voltage control delay line, a delay-locked loop, a self-synchronizing pipeline type digital system, a voltage-controlled oscillator, and a phase-locked loop, constructed using the mentioned semiconductor integrated circuit.
2. Related Background Art
With present progress in the speed-up technology of LSI there are commercially available microprocessors operating at several hundred MHz and LSI for communication in several GHz band. The high-frequency clock synchronization technology is essential to development of the speed-up technology of these developments. Increase in the accuracy and speed of voltage control variable delay circuits is important as the core of the pulse synchronization control technology of PLL, DLL, and so on. A voltage control variable delay circuit is illustrated in
FIG. 1. A
CMOS inverter is constructed of an NMOS transistor
82
and a PMOS transistor
81
, a gate terminal of each transistor being connected to input terminal
1
and a source terminal of each transistor being connected to an input of inverter
88
. An NMOS transistor
83
having a first control terminal
86
as a gate terminal is connected between the ground potential
4
and a source terminal of the NMOS transistor
82
, and a PMOS transistor
84
having a second control terminal
85
as a gate terminal is connected between a power-supply voltage
3
and a source terminal of the PMOS transistor
81
. In this setup, control voltages of the control terminals
85
,
86
are changed, so as to change conductances of the PMOS transistor
84
and NMOS transistor
83
, thereby controlling a delay of a pulse appearing at output terminal
2
.
The voltage control variable delay circuit illustrated in
FIG. 1
, however, had the problem of increase in jitter amounts caused by the differences of delay amounts. This problem will be explained using
FIGS. 2
,
3
, and
4
.
FIG. 2
is a time chart that applies during the pulse delay control of the circuit shown in FIG.
1
. Numeral
89
designates an input signal applied to the input terminal
1
, and a waveform at node
87
varies as indicated by
90
,
91
,
92
while its slewing rate is controlled by the voltages applied to the terminals
85
,
86
. This waveform is binarized by logic threshold
96
of the inverter
88
, whereby a delay is generated. Increase of the delay of output can be realized by controlling the slewing rate from the waveform
90
to
92
of
FIG. 2
, thereby achieving the variable delay circuit having delay amounts D
1
, D
2
, D
3
from output waveforms
93
,
94
,
95
corresponding to the waveforms
90
,
91
,
92
.
FIG. 3
is a diagram for explaining a jitter amount in the case of the waveform
90
, and
FIG. 4
is a diagram for explaining a jitter amount in the case of the waveform
92
. In practical circuits, noise signal
97
consisting of thermal noise of the circuit and external noise, etc., is superimposed on such waveforms. In the case of the delay time D
1
, when the CMOS inverter
88
of the next stage binarizes the signal by the logic threshold
96
, and supposing the noise density of the noise signal
97
is of a Gaussian distribution as shown in
FIG. 3
, a jitter
98
having the width of J
1
appears. When the controlled delay time is changed to D
3
, so as to lower the slewing rate, the signal and noise width across the logic threshold
96
increases as shown in
FIG. 4
, and thus the jitter increases to a jitter
99
having the width of J
2
. Since at least the thermal noise of the circuit is normally present in signals, when the delay is controlled by the above-stated method, the larger the delay, the larger the jitter, which is fluctuation along the time-base direction.
SUMMARY OF THE INVENTION
The present invention has been accomplished in view of the above point to be improved, and an object of the present invention is to provide a semiconductor integrated circuit including a delay circuit without change in the jitter against change in the delay of signal.
Another object of the present invention is to provide a semiconductor integrated circuit that has no dependence of increase or decrease of the jitter on change in the delay, that can achieve low jitter characteristics, that has enhanced high-frequency clock synchronization accuracy, and that permits higher-speed clock control.
Still another object of the present invention is to provide a semiconductor integrated circuit having a number of circuit units for carrying out the voltage control delay, connected in series, the semiconductor integrated circuit being capable of changing the delay in a wide dynamic range of delay-variable region and the semiconductor integrated circuit being capable of configuring a PLL or DLL loop having pulling characteristics of a wide range or a delay line having a wide variable range.
A further object of the present invention is to provide a delay-locked loop, a self-synchronizing pipeline type system, a voltage-controlled oscillator, a phase-locked loop, each having the aforementioned semiconductor integrated circuit.
One aspect of the present invention is to provide a semiconductor integrated circuit comprising a circuit unit, the circuit unit comprising an NMOS transistor and a PMOS transistor connected to each other between gate terminals thereof and between drain terminals thereof. The circuit unit has first and second capacitor means connected in parallel at one terminal of each capacitor means to the gate electrodes of the NMOS transistor and the PMOS transistor connected to each other, the other terminal of the first capacitor means being an input terminal and the other terminal of the second capacitor means being a control terminal. A source terminal of the NMOS transistor is a ground terminal, a source terminal of the PMOS transistor is a power-supply terminal, and the drain terminals of the NMOS transistor and the PMOS transistor connected to each other are an output terminal.
Another aspect of the present invention is to provide a voltage-controlled oscillator comprising a plurality of circuit units, each circuit unit comprising an NMOS transistor and PMOS transistor connected to each other between gate terminals thereof and between drain terminals thereof. First and second capacitor means are connected in parallel at one terminal of each capacitor means to the gate electrodes of the NMOS transistor and the PMOS transistor connected to each other, the other terminal of the first capacitor means being an input terminal and the other terminal of the second capacitor means being a control terminal. A source terminal of the NMOS transistor is a ground terminal, a source terminal of the PMOS transistor is a power-supply terminal, and the drain terminals of the NMOS transistor and the PMOS transistor connected to each other are an output terminal. Also, an output terminal of each circuit unit is connected to an input terminal of a circuit unit of a next stage, an input terminal of the circuit unit of the first stage is connected to an output terminal of the circuit unit of the final stage, the control terminals of the circuit units of the first stage and the final stage are connected to each other, and the control terminals of the circuit units except for the first stage and the final stage are connected to each other.
Further, the present invention provides a circuit wherein many stages of the above-stated semiconductor integrated circuit units are connected in series whereby the circuit is provided with a variable delay in a wide dynamic range of delay variable region; PLL and DLL loops with pulling characteristics of a wide range and a delay line with a wide variable range can be constructed thereby; because the delay value can be controlled by the level shift of waveform, the control characteristics with good linearity can be assured and accurate control can be performed, thus providing th

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