Semiconductor integrated circuit comprising MIS capacitors

Details Semiconductor integrated circuit comprising MIS capacitors Semiconductor integrated circuit comprising MIS capacitors

1995-11-14

2001-07-24

Flynn, Nathan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Passive components in ics

C257S528000, C257S535000

Reexamination Certificate

active

06265755

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit having MIS (metal-insulator silicon) capacitors and also to a semiconductor device having such a circuit.
BACKGROUND OF THE INVENTION
FIG. 5
is a cross-sectional view of main portions of a semiconductor device equipped with a conventional MIS capacitive element. This semiconductor device comprises a substrate on which complementary MOS (CMOS) devices (not shown) are fabricated. This structure comprises the p-type silicon substrate
50
having a region over which the MIS capacitive element is to be formed. An n-type epitaxial layer
51
is formed in this region over the p-type substrate
50
. A LOCOS oxide film
52
is formed on the surface of the epitaxial layer
51
so as to surround both a region in which the bottom electrode of the MIS capacitive element is to be formed and a region in which a contact is to be formed. An n-type doped layer
53
a
for the bottom electrode of the MIS capacitive element and an n-type doped layer
53
b
for the contact are formed in and on the epitaxial layer
51
surrounded by the LOCOS oxide film
52
.
A silicon nitride (SiN) film
54
and a boro-phosphosilicate glass (BPSG)
55
are successively laminated on the LOCOS oxide film
52
so as to cover the surface of the epitaxial layer
51
. In this structure, an oxide film
56
is interposed between the n-type doped layer
53
b
and the SiN film
54
.
Those portions of the BPSG film
55
which are located just above the n-type doped layer
53
a
are removed, thus forming windows
55
a
. An aluminum (Al) electrode
57
a
(first MIS terminal) is formed as a top electrode over the SiN film
55
inside the windows
55
a
. The first MIS terminal
57
a
is formed over the n-type doped layer
53
a
via the SiN film
54
, whereby an MIS capacitor
60
is formed. Contact holes
58
in communication with the n-type doped layer
53
b
are formed in the oxide film
56
, in the SiN film
54
, and in the BPSG film
55
which are located over the n-type doped layer
53
b
. An aluminum (Al) electrode (second MIS terminal)
57
b
is formed over the BPSG film
55
so as to fill in the contact holes
58
. Thus, a contact is formed.
The circuit of the above-described conventional semiconductor device is shown in
FIG. 6. A
parasitic junction capacitance
61
formed between the n-type epitaxial layer
51
and the p-type Si substrate
50
shown in
FIG. 5
exists between a substrate terminal
50
a
and the second MIS terminal
57
b
. Generally, the impedance Z of an RC series circuit decreases as the capacitance C is increased, as given by
Z={R
2
+(1/&ohgr;
C
)
2
}
½
where R is a resistance and &ohgr; is an angular velocity.
Accordingly, if the CMOS devices (not shown) formed on the substrate on which the MIS capacitor
60
is also formed operate, and if digital signals are transmitted to the substrate terminal
50
a
from the CMOS devices, then the digital signals pass through the parasitic junction capacitance
61
and go to the second MIS terminal
57
b
, as indicated by the arrow. As a result, the digital signals, or noises, enter a separate circuit connected with the MIS capacitive element, creating a crosstalk.
SUMMARY OF THE INVENTION
The present invention has been made to solve the foregoing problem.
It is an object of the present invention to provide a semiconductor integrated circuit for preventing crosstalk of a digital signal transmitted to its substrate to other circuit connected with an MIS capacitive element.
It another object of the invention to provide a semiconductor device for preventing crosstalk of a digital signal transmitted to its substrate to other circuit connected with an MIS capacitive element.
A semiconductor integrated circuit according to the present invention comprises a substrate terminal, an MIS capacitor, a first capacitor, a second capacitor, and a power supply. The first and second capacitors are connected in series between the substrate terminal and the MIS capacitor. The power supply is connected between the first and second capacitors and controls the potential between the first and second capacitors to a desired potential.
A semiconductor device according to the invention is fabricated in the manner described now. A first layer is formed on a semiconductor base in such a way that the first layer is electrically insulated from the base. A second layer consisting of a dielectric material is formed on the first layer. An MIS capacitor is formed on the second layer. A bottom electrode having a desired pattern is formed on the second layer. A top electrode is formed over the bottom electrode via a dielectric film, thus forming the MIS capacitor. Contact holes reaching the first layer are formed in the second layer and in the dielectric film outside the region where the MIS capacitor is formed. A potential control electrode connected with the power supply is formed on the dielectric film so as to cover the inner surfaces of the contact holes. In this way, the first layer is controlled to any arbitrary potential.
For example, a semiconductor layer or dielectric layer of the opposite conductivity type to the semiconductor base is used as the first layer.
In the novel circuit, the potential between the first and second capacitors is controlled to any arbitrary value by the power supply and, therefore, even if a digital signal coming from other device is transmitted to the substrate terminal, the signal is withdrawn by the power supply through the first capacitor. Consequently, the digital signal which is transmitted to the substrate terminal and passed through the first capacitor is prevented from passing through the second capacitor; otherwise the signal would enter the MIS terminal connected between the second capacitor and the MIS capacitor.
In the novel device, the first capacitor is formed between the semiconductor base and the first layer. The second capacitor is formed between the first layer and the bottom electrode by the second layer made from a dielectric material. The first layer is connected with the potential control electrode which is formed so as to cover the inner surfaces of the contact holes. Therefore, the first layer is controlled to any desired potential. Consequently, even if a digital signal transmitted to the semiconductor base passes through the first capacitor, the signal is removed by the potential control electrode from the first layer. Hence, the digital signal does not enter the contact connected with the first layer.
Other objects and features of the invention will appear the course of the description thereof, which follows.


REFERENCES:
patent: 5124761 (1992-06-01), Senuma et al.
patent: 5395782 (1995-03-01), Ohkoda et al.
patent: 5414291 (1995-05-01), Miwa et al.
patent: 0188353 (1987-08-01), None
patent: 0029962 (1988-02-01), None
patent: 0196583 (1992-07-01), None

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