Semiconductor integrated circuit chip-to-chip interconnection sc

Details Semiconductor integrated circuit chip-to-chip interconnection sc Semiconductor integrated circuit chip-to-chip interconnection sc

1988-07-21

1990-06-26

Hille, Rolf

357 74, 357 75, 357 79, H01L 2348, H01L 2302, H01L 2316, H01L 2342

Patent

active

049376535

ABSTRACT:
Integrated circuit chip-to-chip interconnections are made via gold pads on each chip that are bonded to corresponding gold pads on a silicon wafer chip carrier. The pads on the chips and/or the pads on the carrier are characterized by texturing (roughening) with a feature size of the order of a micrometer or less, so that each of the pads on the chip can be attached to each of the pads on the carrier by compression bonding at room temperature--i.e., cold-well bonding. In particular, the texturing of the gold pads on the silicon carrier is obtained by etching V-grooves locally on the surface of the underlying silicon carrier in the regions of the pads, thermally growing a silicon dioxide layer on the silicon carrier, and depositing the gold on the silicon dioxide layer.

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patent: 4670770 (1987-06-01), Tai
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P. Kraynak, "Wafer-Chip Assembly for Large-Scale Integration," IEEE Transactions on Electron Devices, vol. ED-15, pp. 660-663 (1968).
R. F. Tylecote, The Solid Phase Welding of Metals, pp. 189-193 (1968).
G. A. Kennedy, Welding Technology, p. 15 (1974).

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