Semiconductor integrated circuit capable of controlling read...

Details Semiconductor integrated circuit capable of controlling read... Semiconductor integrated circuit capable of controlling read...

2009-06-29

2011-11-01

Nguyen, Van Thu (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S189120, C365S230080, C365S233100, C365S233180

Reexamination Certificate

active

08050137

ABSTRACT:
The semiconductor integrated circuit includes a command decoder, a shift register unit and a command address latch unit. The command decoder is responsive to an external command defining write and read modes and configured to provide a write command or a read command according to the external command using a rising or falling clock. The shift register unit is configured to shift an external address and the write command by a write latency in response to the write command. The column address latch unit is configured to latch and provide the external address as a column address in the read mode, and to latch a write address, which is provided from the shift register unit, and provide the write address as the column address in the write mode.

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patent: 6549452 (2003-04-01), Park
patent: 7162657 (2007-01-01), Takahashi et al.
patent: 7221618 (2007-05-01), Kim
patent: 7447108 (2008-11-01), Choi
patent: 7653780 (2010-01-01), Takahashi
patent: 2009/0040844 (2009-02-01), Choi
patent: 2006-190434 (2006-07-01), None
patent: 100574108 (2006-04-01), None
patent: 1020080002492 (2008-01-01), None

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