Semiconductor integrated circuit boundary scan test with multipl

Details Semiconductor integrated circuit boundary scan test with multipl Semiconductor integrated circuit boundary scan test with multipl

1991-12-02

1993-07-06

Williams, Howard L.

Coded data generation or conversion

Converter calibration or testing

371 221, 324158R, H03M 110, G01R 3128

Patent

active

052258343

ABSTRACT:
A semiconductor integrated circuit having a test circuit built therein is disclosed which consists of an A/D converter to be connected to a peripheral circuit, a digital circuit connected to the A/D converter, a digital signal switching device for selectively connecting to the output of the A/D converter and that of the digital circuit, and a boundary scan output circuit connected to the output of the digital signal switching device, wherein the digital signal switching device connects the A/D converter to the boundary scan output circuit in a normal mode, while the signal fetched in the boundary scan output circuit is outputted therefrom in test mode. Semiconductor integrated circuits having an analog circuit built therein and an analog integrated circuit in which a test circuit is built-in are also disclosed.

REFERENCES:
patent: 4872169 (1989-10-01), Whetsel, Jr.
patent: 4922492 (1990-05-01), Faseng et al.
patent: 4967142 (1990-10-01), Sauerwald et al.
patent: 5132685 (1992-07-01), De Witt et al.
patent: 5132974 (1992-07-01), Rosales
patent: 5150044 (1992-09-01), Hashizume et al.
IEEE Standard Test Access Port and Boundary-Scan Achitecture, IEEE Standard 11.49.1-1990.

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