Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays
Reexamination Certificate
2000-07-11
2003-02-25
Ho, Hoai (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
C257S206000, C257S207000, C257S209000, C257S210000, C257S208000
Reexamination Certificate
active
06525350
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
This invention relates to a small area basic cell used in semiconductor integrated circuit.
2. Description of Related Art
There are several kinds of semiconductor integrated circuits. More particularly, Application Specific Integrated Circuits (ASIC), whose design is based on functions required by a user, includes gate array and cell-based schemes. In gate array semiconductor integrated circuits, a master slice is manufactured in advance which is common up to a transistor forming process. Then, it is customized at a metal wiring process depending on functions required by a user to provide a user-desired semiconductor integrated circuit in a reduced time and cost. The master slice includes a cell array, in which basic cells are regularly arranged in an array, on a surface of a semiconductor substrate. Here, the basic cell includes a plurality of transistors as basic units.
In this customizing scheme, photomasks designed and produced depending on functions needed by a user are used for the metal wiring processes. The gate array scheme also includes another customizing scheme where connections between the basic units are changed by using an energy beam such as a laser beam.
In the cell-based scheme, customization is implemented from transistor forming processes in order to provide a high density and high performance semiconductor integrated circuit. In this case, standard cells such as basic gates and a flip-flop, macro cells such as a memory and a multiplier, and/or mega cells such as a CPU and a DSP core, are designed and prepared in a cell library in advance, and then are combined in order to design an integrated circuit, which implements functions needed by a user.
Other kinds of ASICs include a Programmable Logic Device (PLD) such as a Field Programmable Gate Array (FPGA), and a Complex Programmable Logic Device (CPLD). In PLDs, a product manufactured according to a certain specification is purchased by a user and programmed according to functions needed by the user. In FPGAs, an array of programmable basic cells (also called Programmable Logic Elements, Configurable Logic Blocks, or the like) and programmable wiring are formed on a semiconductor substrate and programmed by a user.
FIG. 15
shows a plan view of a layout of an exemplary basic cell used in a conventional gate array integrated circuit. As shown, three basic cells
72
(cells
72
a
,
72
b
and
72
a
are shown) having the same configuration are arranged in line in the lateral direction of the figure. Each of basic cells
72
includes four P-type transistors
12
(including two large transistors
12
a
and two small transistors
12
b
), and two N-type transistors
14
. The p-type transistors comprise a P-type active region
16
, which is formed within an N-well (not shown) on a surface of the semiconductor substrate, and two common gate electrodes,
20
a
and
20
b
, which are placed over the P-type active region
16
. The N-type transistors
14
comprise an N-type active region
18
, which is formed within a P-well (not shown) and two common gate electrodes,
20
a
and
20
b
, which are placed over the N-type active region
18
. On both sides of the gate electrodes of the P-type and N-type active regions are formed N-type and P-type diffusion regions, respectively. Those diffusion regions form sources and drains of the transistors.
On the surface of the active region, which is overlapped with the gate electrode, is formed a channel of the transistor. The width and length of the gate electrode in the area overlapping the active region determine a channel length and a channel width of the transistor. Usually, the width of the gate electrode in this area, which determines the channel length of the transistor, is formed to be a minimum width, which may be manufactured by a process technology used to manufacture the semiconductor integrated circuit. A current driving capacity of the transistor is determined by a ratio of the channel width and the channel length. Because the channel length is determined by the process technology to be used, it is necessary to increase a dimension of the active region in the direction where the gate electrode extends (the dimension in the vertical direction in the case of the basic cell in
FIG. 15
) and to increase the channel width. It increases the driving capacity of the transistor and provides a semiconductor integrated circuit which can operate with a higher frequency.
In the plane view layout of
FIG. 15
, a power supply line
24
is placed on the upper side of the P-type transistors
12
a
,
12
b
, and a ground line
26
is placed on the lower side of the N-type transistor
14
in the lateral direction, respectively. The power supply line
24
and the ground-line
26
are formed in the first metal wiring layer (M
1
). The power supply line
24
is used for supplying a power supply potential to the transistors. The ground line
26
is used for supplying a ground potential to the transistors. Though not shown, a power supply potential and a ground potential are also supplied to the N- and P-wells.
The power supply line
24
and the ground line
26
(referred to together as “power bus wiring” hereinafter) have not formed yet in the master slice where processes up to the transistor forming process have been completed. However, the power bus lines are also parts of the basic cell in that they are formed in the same pattern regardless of the function needed by a user.
Further, in the basic cells
72
a
,
72
b
, two N-type transistors
22
are placed on the lower side of the ground line
26
.
Cross symbols (+) shown in
FIG. 15
indicate boundaries between basic cells. As shown, the basic cells
72
a
and
72
b
form a layout where they are mirror-inverted with respect to a vertical boundary line. They have the same configuration in that they include the same number of transistors having the same dimensions (channel widths and channel lengths) and conductive types. In a practical case, basic cells, which are mirror-inverted in the vertical direction as well, are placed to form a cell array.
Black dots (•) shown are grid points
34
provided with a fixed pitch in the lateral and vertical directions. The grid points
34
are virtual points, which are used as a reference for positioning various components. Such points do not exist in an actual semiconductor integrated circuit. For example, contacts may be placed on the grid points
34
, which are for connecting source and drain diffusion regions and gate electrodes
20
a
,
20
b
of the P-type and N-type transistors with wires in M
1
layer placed on the interlayer insulating film over the transistors.
The pitch between the grid points is determined by the process technology to be used for semiconductor integrated circuit manufacturing. For example, the distance between centers of two contacts placed on diffusion regions on both sides of the gate electrode must be equal to, or larger than, a value determined by the sum of twice the distance between the gate electrode and the contact, which is needed for preventing a short between the gate electrode and the contact, and a width of the gate electrode and a dimension of a contact. For example, in a manufacturing process with a design rule (generally indicated by a minimum width of a gate electrode) of 0.25 &mgr;m, when the gate electrode width and the contact dimension are assumed to be minimum, the minimum distance is 1.04 &mgr;M where the gate electrode width, the contact dimension (the length of one side of a square) and the space between the gate electrode and the contact are 0.24 &mgr;m, 0.32 &mgr;m, and 0.24 &mgr;m, respectively.
The pitch of the grid points
34
in
FIG. 15
is set to the minimum value of 1.04 &mgr;m in order to allow for positioning of the contacts at arbitrary grid points.
Grid points
34
are positioned in the same pitch over a whole area within the cell array region where basic cells
72
a
,
72
b
are placed in the vertical and horizontal directions. However, the pitch in the vertical direction betwee
Kinoshita Eita
Mizuno Makoto
Ho Hoai
Kawasaki Steel Corporation
Le Thao P
Oliff & Berridg,e PLC
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