Semiconductor integrated circuit and wiring method

Details Semiconductor integrated circuit and wiring method Semiconductor integrated circuit and wiring method

1980-10-15

1983-10-25

Davie, James W.

357 68, H01L 2700

Patent

active

044122403

DESCRIPTION:

BRIEF SUMMARY
DESCRIPTION

1. Technical Field
The present invention relates to a semiconductor integrated circuit, and more particularly to a large scale integrated circuit and wiring method suited to automatic designing.
2. Background Art
As is well known, the density of an integrated circuit (IC) structure is increasing and resultingly layout of an IC can be made in a unit of a circuit (called a "cell") such as a NAND gate or flip-flop instead of a transistor, and wiring is carried out by the grid system where connection between cells can be established. Thereby, the amount of information considered at the time of designing can be reduced and the processing rate can also be improved. In this grid wiring system, the layout space is partitioned in the form of a grid with the dimensions larger than the minimum dimension for patterning the wiring material layer in fabrication of ICs, for example, by the vertical and horizontal lines having the interval of the wiring pitch dimensions (in actuality that interval multiplied by the reduction scale), and the wiring pattern is depicted on such vertical and horizontal lines. The wiring pitch differs in accordance with the wiring layer location such as 1st or 2nd layers and the wiring material such as aluminium, polysilicon or diffusion layer. For example, in the case of 1st layer wiring of aluminium, the allowable minimum line interval is 10 .mu.m; or in the case of polysilicon it is 10 .mu.m, while that of the 2nd layer of aluminium is 15 .mu.m. Here, the existing grid employs the rectangular mesh having a horizontal line interval of 10 .mu.m and vertical line interval of 15 .mu.m. Use of this grid allows drawing of the wiring pattern of the 1st layer (with the allowable minimum line interval) correctly only by depicting the lines indicating the wiring on the horizontal lines, and also allows drawing of the wiring pattern of the 2nd layer correctly only by depicting the lines indicating the wiring on the vertical lines. Thus, a mask can be generated on the basis of this grid and wiring of the IC can be obtained through the photo process, etc.
Before employing the grid system for designing the semiconductor device, usually the section paper forming a square mesh with equal horizontal and vertical line intervals has been used in order to depict the wiring pattern. Namely, the lines indicating wirings were are drawn on the horizontal or vertical lines of this section paper or between the horizontal and vertical lines. Then, such drawing is reduced, for example, to the scale of 1/1000 (when the mesh has an interval of 1 mm, it is reduced up to 1 .mu.m or 0.5 .mu.m which almost corresponds to the minimum dimensions of the patterning) in order to obtain the mask. In this method using such section paper, it is required to check if the interval between wiring patterns depicted is larger than the allowable minimum line interval or not, and this check is very troublesome when an IC has succeeded in achieving greater density.
Considering this point, the grid system is very convenient and the wiring interval always becomes broader than the allowable minimum line interval when a rule that the wiring should always be depicted on the grid (vertical, horizontal lines) is observed. Therefore, the line interval check is not required in the grid system. However, in the existing grid system, for example, the horizontal line is used for the 1st layer individually, while the vertical line is used for the 2nd layer (thereby the allowable minimum line interval of each layer can be reserved easily). In case where the cells 1 and 2 exist as shown in FIG. 1 and wiring is established between these cells and thereby the wirings 3, 4, 5 must be bent at the portions a and b, the 1st layer wiring should be connected to the 2nd layer wiring at the portion a, while the 2nd wiring should be connected to the 1st layer wiring again at the portion b. Thus the 1st layer and 2nd layer wirings are connected at the points a and b via through holes. This wiring method is very complicated, requiring wider wiring areas an

REFERENCES:
patent: 4278897 (1981-07-01), Ohno et al.
patent: 4295149 (1981-10-01), Balyoz et al.

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