Semiconductor integrated circuit and unstable bit detection...

Details Semiconductor integrated circuit and unstable bit detection... Semiconductor integrated circuit and unstable bit detection...

2008-12-19

2011-12-20

Lappas, Jason (Department: 2827)

Static information storage and retrieval

Floating gate

Particular connection

C365S189150, C365S196000, C365S207000

Reexamination Certificate

active

08081510

ABSTRACT:
A semiconductor integrated circuit including a nonvolatile memory cell is provided with a detection/word line voltage control circuit for sequentially supplying two or more mutually different unstable bit detecting voltages to a control gate of the nonvolatile memory cell to cause the nonvolatile memory cell to output a plurality of pieces of readout data, and an OK/NG determination circuit for comparing the plurality of pieces of readout data to determine whether the nonvolatile memory cell is stable or not.

REFERENCES:
patent: 2004/0008544 (2004-01-01), Shinozaki et al.
patent: 8-178976 (1996-07-01), None
patent: 2005-222202 (2005-08-01), None

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