Semiconductor integrated circuit and system

Details Semiconductor integrated circuit and system Semiconductor integrated circuit and system

1999-09-09

2004-01-20

Nadav, Ori (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257S786000, C257S386000

Reexamination Certificate

active

06680543

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a semiconductor integrated circuit and system for reducing a power loss and noise caused by a parasitic element of a bonding pad, and specifically a semiconductor integrated circuit and system having a pad structure suitable for inputting and outputting a signal having a high frequency.
BACKGROUND ART
In the field of computers, the clock frequency has been increased in order to operate the computers at a higher speed. This requires memories and other peripheral devices to input and output a signal having a higher frequency in order to realize a higher speed interface.
Communication systems are also required to have a capability of inputting and outputting a signal having a higher frequency at a lower power loss and lower noise. For example, digital cell phones such as PHS phones use a signal having a frequency of 1 GHz to 2 GHz. Accordingly, it is required to transmit and receive such a signal at a lower power loss and with lower noise.
FIG. 20
shows a structure of a conventional communication system
200
. The communication system
200
includes an RF section
210
for transmitting or receiving a signal and a baseband signal processing section
220
for processing a signal to be transmitted or a signal received. Conventionally, the RF section
210
and the baseband signal processing section
220
are formed on different chips. For example, the RF section
210
is formed on a GaAs substrate, and the baseband signal processing section
220
is formed on a silicon substrate.
A signal received by an antenna
201
is input to a low noise amplifier (LNA)
211
of the RF section
210
through a transmitting/receiving switch
202
. The LNA
211
amplifies the received signal. The amplified signal is input to a mixer
213
though a filter
212
. The mixer
213
mixes the signal output from the filter
212
and an oscillation signal output from an oscillator
214
. The output from the mixer
213
is supplied to the baseband signal processing section
220
.
The baseband signal processing section
220
includes a converter
221
and a digital signal processor (DSP)
222
. The converter
221
converts the analog signal output from the mixer
213
into a digital signal. The DSP
222
processes the digital signal.
The digital signal processed by the DSP
222
is converted into an analog signal by the converter
221
. A mixer
215
of the RF section
210
mixes the signal output from the converter
221
and an oscillation signal output from the oscillator
214
. A power amplifier (PA)
216
amplifies the output from the mixer
215
. The amplified signal is transmitted from the antenna
201
through the transmitting/receiving switch
202
.
FIG. 21
schematically shows an equivalent circuit from the antenna
201
to the LNA
211
. In
FIG. 21
, the transmitting/receiving switch
202
is omitted. The antenna
201
is connected to a bonding pad
103
through a signal line
217
. The bonding pad
103
is connected to an input section of the LNA
211
through a signal line
218
. Thus, a signal received by the antenna
201
is input to the LNA
211
through the bonding pad
103
.
FIG. 22
shows a semiconductor circuit
100
including the bonding pad
103
. The semiconductor circuit
100
includes a semiconductor substrate
101
, an insulating layer
102
formed on the semiconductor substrate
101
, and the bonding pad
103
formed on the insulating layer
102
. On the semiconductor substrate
101
, a MOS transistor
113
is also formed. Herein, it is assumed that the MOS transistor
113
is included in the input section of the LNA
211
. A signal received by the antenna
201
is input to the bonding pad
103
as a voltage signal V
in
. The bonding pad
103
is connected to a gate of the MOS transistor
113
. Accordingly, the voltage signal V
in
is applied to the gate of the MOS transistor
113
.
FIG. 23
shows an equivalent circuit of the semiconductor circuit
100
shown in FIG.
22
. In
FIG. 23
, C
p
represents a parasitic capacitance existing between the bonding pad
103
and the semiconductor substrate
101
, and R
p
represents a parasitic resistance existing on a current path from the bonding pad
103
to a ground potential.
The impedance Z of the bonding pad
103
is represented by expression (1).
Z=
(1/
j&ohgr;C
p
)+
R
p
  expression (1)
Herein, C
p
represents a parasitic capacitance, and R
p
represents a parasitic resistance. Letter j is a symbol indicating an imaginary number. &ohgr;=2&pgr;f, and f represents a frequency of the signal input to the bonding pad
103
.
A power loss is generated by the impedance Z of the bonding pad
103
.
The power loss P
a
based on the impedance Z of the bonding pad
103
is represented by expression (2).
P
a
=&ohgr;
2
C
p
2
R
p
|V
in
|
2
/(1+&ohgr;
2
C
p
2
R
p
2
)  expression (2)
Herein, V
in
represents a voltage applied to the bonding pad
103
.
FIG. 24
shows the relationship among the parasitic resistance R
p
, the parasitic capacitance C
p
and the power loss P
a
. In
FIG. 24
, it is assumed that the frequency f of the signal input to the bonding pad
103
is 1 GHz.
In the conventional communication system
200
, when the RF section
210
including the bonding pad
103
is formed on the GaAs substrate, the power loss P
a
is hardly a problem because the parasitic resistance R
p
is sufficiently large due to a very large resistance of the GaAs substrate.
However, the GaAs substrate is very expensive. Furthermore, when the RF section
210
is formed on the GaAs substrate, the RF section
210
and the baseband signal processing section
220
need to be formed on different chips from each other since it is preferable that the baseband signal processing section
220
is formed on a silicon substrate suitable for fabrication of a CMOS structure. This causes a problem that it is difficult to reduce the cost by forming main parts of the communication system
200
on a single chip.
When the RF section
210
and the baseband signal processing section
220
are formed on a single silicon chip, the parasitic capacitance C
p
is about 1 pF and the parasitic resistance R
p
is about 100 &OHgr;. Therefore, the power lose based on the parasitic element of the bonding pad
103
is about several times as large as the power loss generated in the MOS transistor
113
(see FIG.
24
). Accordingly, when the RF section
210
is formed on a silicon chip, the parasitic resistance R
p
needs to be reduced.
It is understood from
FIG. 24
that the power loss P
a
can be reduced also by reducing the parasitic capacitance C
p
. In order to reduce the parasitic capacitance C
p
, the size of the bonding pad
103
needs to be reduced or the thickness of the insulating layer
102
needs to be increased. In consideration of the precision of the wire bonding, the size of the bonding pad
103
can only be reduced to a limited extent. It is difficult to increase the thickness of the insulating layer
102
in consideration of the other circuit elements formed on the semiconductor substrate
101
. As can be appreciated, it is not very practical to reduce the power loss P
a
by reducing the parasitic capacitance C
p
. Accordingly, it is desirable to reduce the parasitic resistance R
p
without substantially increasing the parasitic capacitance C
p
.
FIG. 25
shows the relationship between the frequency f of the signal input to the bonding pad
103
and the power loss P
a
. It is understood from
FIG. 25
that, as the frequency of the signal input to the bonding pad
103
is increased, the parasitic resistance R
p
needs to be reduced by a greater degree.
The parasitic resistance R
p
also significantly influences the noise characteristic of the MOS transistor
113
connected to the bonding pad
103
. The minimum noise F
min
of the MOS transistor
113
is generally represented by expression (3), which is referred to as the “fukui” equation.
F
min
=1+2&pgr;
fKC
gs
((
R
g
+R
s
/gm
)  expression (3)
Herein, C
gs
, represents a gate-source cap

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