Static information storage and retrieval – Addressing – Including particular address buffer or latch circuit...
Reexamination Certificate
2011-03-01
2011-03-01
Phung, Anh (Department: 2824)
Static information storage and retrieval
Addressing
Including particular address buffer or latch circuit...
C365S189050
Reexamination Certificate
active
07898899
ABSTRACT:
The semiconductor integrated circuit comprises: a first buffer circuit that outputs a first output signal to an output terminal on receipt of a first input signal; a second buffer circuit that includes a circuit having a similar configuration to the first buffer circuit, that outputs a second output signal on receipt of the first input signal, and that outputs the second output signal based on a check signal; a third buffer circuit that outputs a third output signal based on the check signal; a determination circuit that receives the second output signal and the third output signal and activates a detection signal, in response to the detection that the second output signal is behind the third output signal; and a fourth buffer circuit that operates during the activation of the detection signal and outputs the third output signal to the output terminal, on receipt of the first input signal.
REFERENCES:
patent: 6166990 (2000-12-01), Ooishi et al.
patent: 6897695 (2005-05-01), Arai
patent: 6925023 (2005-08-01), Mizugaki et al.
patent: 2007/0101177 (2007-05-01), Kuroki
patent: 2004-187219 (2004-07-01), None
Arent & Fox LLP
Fujitsu Semiconductor Limited
Phung Anh
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