Semiconductor integrated circuit and semiconductor memory...

Details Semiconductor integrated circuit and semiconductor memory... Semiconductor integrated circuit and semiconductor memory...

2002-09-18

2004-07-06

Zweizig, Jeffrey (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

Reexamination Certificate

active

06759896

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application P2001-290131 filed on Sep. 21, 2001; the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1 . Field of the Invention
The present invention relates to a semiconductor integrated circuit and semiconductor memory. In particular, it relates to a semiconductor integrated circuit and semiconductor memory including a voltage step-down circuit, which steps down an external power supply voltage to an internal power supply voltage, supplying an internal circuit.
2. Description of the Related Art
In response to recent improvements in microfabrication technology, techniques for achieving high integration and speed by setting the internal power supply voltage to be lower than the external power supply voltage, have been actively studied. The voltage step-down circuit is a fundamental technical element stepping down the external power supply voltage to the internal power supply voltage. The internal power supply voltage is to be supplied to the internal circuit. The external power supply voltage is supplied from a power supply terminal on a semiconductor chip.
The voltage step-down circuit includes a comparator circuit and a p-type MOS transistor, which is driven by the external power supply voltage. The comparator circuit controls the gate voltage of the p-type MOS transistor. The internal power supply voltage is supplied from the drain electrode of the p-type MOS transistor under gate control by the comparator circuit. There is an internal capacitance between the internal power supply voltage and ground potential. The internal power supply voltage is supplied to the internal circuit, which consumes electric current.
As illustrated in
FIG. 1
, when the internal circuit changes from a standby state
10
to an active state
11
, current dissipation IDD of the internal circuit changes greatly. The change in current dissipation IDD causes fluctuation in the internal power supply voltage VINT, interfering with the high-speed operation of the internal circuit. Fluctuation in the internal power supply voltage VINT is greatest immediately after changing from the standby state
10
to the active state
11
, and then gradually decreases.
In order to reduce fluctuation in the internal power supply voltage VINT, an increase in internal capacitance, or the enlargement of the comparator circuit and p-type MOS transistor is necessary. However, the increasing the internal capacitance is not easy due to limitations in chip area. The enlargement of the comparator circuit and p-type MOS transistor causes an increase in current consumption of the voltage step-down circuit itself, which is undesirable.
Considering a steady supply of internal power supply voltage VINT, a “stop clock” technique is used, whereby a plurality of voltage step-down circuits are uniformly distributed within the semiconductor chip, some step-down circuits are halted in the standby state, reducing the overall current consumption of the step-down circuits. However, while the “stop clock” technique may reduce step-down circuit current consumption in the standby state, the “stop clock” technique does not allow the reduction of step-down circuit current consumption in an active state.
SUMMARY OF THE INVENTION
A first aspect of the present invention provides a semiconductor integrated circuit including an internal circuit, a transition state voltage step-down circuit generating an internal power supply voltage supplied to the internal circuit from an external power supply voltage only for a fixed time period after the internal circuit is changed from a standby state to an active state, and a steady state voltage step-down circuit generating the internal power supply voltage from the external power supply voltage for duration that the internal circuit is in either the standby state or the active state.
A second aspect of the present invention provides a semiconductor memory including a memory circuit, a transition state voltage step-down circuit generating an internal power supply voltage supplied to the memory circuit from an external power supply voltage only for a fixed time period after the memory circuit is changed from a standby state to an active state, and a steady state voltage step-down circuit generating the internal power supply voltage from the external power supply voltage for duration that the memory circuit is in either the standby state or the active state.


REFERENCES:
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patent: 5337284 (1994-08-01), Cordoba et al.
patent: 5352935 (1994-10-01), Yamamura et al.
patent: 6172932 (2001-01-01), Kim
patent: 6313694 (2001-11-01), Sohn
patent: 6342808 (2002-01-01), Bae
patent: 07-085678 (1995-03-01), None
patent: 10-208467 (1998-08-01), None

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