Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Current driver
Reexamination Certificate
2001-02-28
2002-08-13
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Current driver
C257S371000
Reexamination Certificate
active
06433594
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit and a semiconductor integrated circuit system capable of completely cutting off a current flowing to and from the outside when a supply of a power source voltage is stopped.
BACKGROUND OF THE INVENTION
Among one-chipped semiconductor integrated circuits and semiconductor integrated circuit systems having a plurality of such semiconductor integrated circuits provided on the same one printed circuit board, some of them are equipped with means for stopping a power source of a part of the semiconductor integrated circuits in order to eliminate power that is consumed in non-operating circuit portions. Particularly, it is essential that such means are loaded onto the semiconductor integrated circuits or the semiconductor integrated circuit systems that are operated by batteries as their power source.
FIG. 11
is a block diagram showing a schematic configuration of a conventional representative semiconductor integrated circuit system. In
FIG. 11
, a semiconductor integrated circuit system has peripheral ICs
1
to
3
, a CPU
4
and a memory
5
structured as a plurality of semiconductor integrated circuits. Particularly, these semiconductor integrated circuits carry out data input/output via a bus
6
pulled up to a high power source voltage by a pull-up resistor
7
.
In the system having this structure, it is not necessary to keep the peripheral ICs
1
to
3
operated at all times. Therefore, the power supply to all or a part of the peripheral ICs
1
to
3
is cut off during a specific period, thereby to save power.
FIG. 12
is a diagram for explaining the operation of a signal output circuit of the conventional peripheral IC. In
FIG. 12
, a peripheral IC
1
has a power source terminal
200
and an output terminal
201
connected to a data bus
6
. Inside this peripheral IC
1
, there is provided a signal output circuit that consists of a PMOS transistor
202
having its source connected to the power source terminal
200
and its drain connected to the output terminal
201
, an NMOS transistor
203
having its source grounded and its drain connected to the output terminal
201
, a NAND gage
204
, an NOR gate
205
, and an inverter
206
.
The NAND gate
204
inputs an output enable signal to one input terminal, inputs output data to the other input terminal, and connects an output terminal to the gate of the PMOS transistor
202
. The inverter
206
inputs the output enable signal, and applies its inverted output to one input terminal of the NOR gate
205
. The NOR gate
205
has an input of the above output data to the other input terminal, and connects its output terminal to a gate of the NMOS transistor
203
.
Based on the above structure, this signal output circuit operates as follows. When the output enable signal is at low logical level (hereafter logic level “L”), the PMOS transistor
202
and the NMOS transistor
203
are both turned OFF. In other words, a signal output from the output terminal
201
of the peripheral IC
1
becomes in an undefined state regardless of the logic level of the output data. On the other hand, when the output enable signal is at high logical level (hereafter logic level “H”) and also when the output data is at the logic level “H”, the PMOS transistor
202
becomes in the ON state and the NMOS transistor
203
becomes in the OFF state. Therefore, a potential equal to the power source voltage supplied to the power source terminal
200
is applied to the output terminal
201
, and the logic level “H” is output.
Further, when the output enable signal is at the logic level “H” and also when the output data is at the logic level “L”, the PMOS transistor
202
becomes in the OFF state and the NMOS transistor
203
becomes in the ON state. Therefore, the potential of the output terminal
201
becomes equal to the ground potential, and the logic level “L” is output. In other words, when the output enable signal is at the logic level “H”, a signal of the logic level shown by the output data is output straight from the output terminal
201
via the drain to which the PMOS transistor
202
and the NMOS transistor
203
are mutually connected.
FIG. 13A
is a circuit diagram, and
FIG. 13B
is a layout cross-sectional diagram of the PMOS transistor that constitutes a signal output circuit in a semiconductor integrated circuit and other PMOS transistor both of which are supplied with a power source voltage by a common power source, in the conventional peripheral IC. As shown in
FIG. 13A
, the PMOS transistor
202
that constitutes the signal output circuit has its source connected to the power source terminal
200
. This power source terminal
200
is also connected to other PMOS transistor
313
that constitutes a circuit other than the signal output circuit.
In other words, the power source terminal
200
is usually connected to many MOS transistors as a common power supply portion for all circuit blocks within the semiconductor integrated circuit.
FIG. 13B
shows this relationship as a layout cross-sectional diagram.
As shown in
FIG. 13B
, the PMOS transistors
202
and
313
are formed in a common N-well area
301
on a P-type semiconductor substrate
300
. The PMOS transistor
202
has a drain and a source formed by P-diffusion areas
306
and
307
respectively, has a back gate formed by an N-diffusion area
305
, and has the output terminal
201
and the drain electrically connected to each other by an aluminum wiring
312
. The wiring of a gate
308
is omitted from the drawing.
The PMOS transistor
313
has a source and a drain formed by P-diffusion areas
302
and
303
respectively, has a back gate formed by an N-diffusion area
304
, and has a wiring drawn from the drain by an aluminum wiring
310
. The wiring of a gate
309
is omitted from the drawing. The source and the back gate of these PMOS transistors are connected to each other by a common aluminum wiring
311
. This aluminum wiring
311
is connected to the power source terminal
200
.
When the supply of the power source voltage has been cut off for energy saving as described above, this means that the power supply to the peripheral IC
1
has been cut off by turning OFF a power supply switch
100
as power supply control unit in FIG.
12
. However, when the power supply has been cut off in this way, the potentials of all the nodes inside the peripheral IC
1
become in an unpredictable state (a high impedance state). In other words, it becomes impossible to guarantee the state of the output voltage of the NOR gate
205
in
FIG. 12
, and the NMOS transistor
203
is not completely turned OFF.
In the state that the power supply has been cut off as described above, the data bus
6
connected to the output terminal
201
is generally pulled up to the logic level “H” by the pull-up resistor
7
. Therefore, there has been a problem in that unnecessary leakage current flows into the peripheral IC
1
from this data bus
6
via the NMOS transistor
203
that has been turned OFF in not a completely OFF state.
This means that, in
FIG. 13
, the signal at the logic level “H” on the data bus
6
flows from the output terminal
201
to the aluminum wiring
312
, the P-diffusion area
307
, the N-well area
301
, the N-diffusion area
305
, and to the aluminum wiring
311
, in this order. As the aluminum wiring
311
is a power source wiring common to other MOS transistors, the signal at the logic level “H” is transmitted to those other MOS transistors that are connected to this aluminum wiring
311
. This means that, in
FIG. 13B
, a high power source voltage Vcc is practically applied to the source of the other PMOS transistor
313
within the same N-well area
301
.
In other words, there has been a problem that when the data bus
6
is at the logic level “H”, even when the power source voltage has not been supplied, the substantially high power source voltage Vcc is supplied to some transistors within the peripheral IC
1
, which results in an unnecessary power consumption and a leakage of the current.
FIG.
Leydig,Voit & Mayer, Ltd.
Nguyen Linh
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