Semiconductor integrated circuit and phase locked loop circuit

Details Semiconductor integrated circuit and phase locked loop circuit Semiconductor integrated circuit and phase locked loop circuit

2001-04-18

2002-09-24

Mis, David (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular frequency control means

C331S008000, C331S017000, C331S057000, C331S175000, C331S17700V, C331S186000, C327S156000, C327S543000

Reexamination Certificate

active

06456166

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATIONS
The subject application is related to subject matter disclosed in Japanese Patent Application No. 146423/2000 filed on May 18, 2000 in Japan to which the subject application claims priority under Paris Convention and which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and a phase locked loop circuit used to a voltage control oscillator and so on.
2. Related Background Art
A phase locked loop (PLL) circuit is used to various applications, because it is possible to easily realize IC implementation and generate an oscillating signal with a high degree of accuracy. The PLL circuit is provided with a VCO (Voltage Control Oscillator). The VCO performs control to change frequency of oscillating signal, based on a control voltage signal in accordance with phase difference between a reference signal and a feedback signal. More specifically, the frequency of the oscillating signal is controlled so that phases of the reference signal coincides with that of the feedback signal.
FIG. 1
is a circuit of a conventional VCO. The VCO of
FIG. 1
has a current generator composed of a PMOS transistor (first transistor) connected between a power supply terminal VDD and a node N
1
, a PMOS transistor (second transistor) Q
2
connected between the node N
1
and an output terminal OUT, a PMOS transistor (third transistor) Q
3
connected between the node N
1
and the other terminal OUTn, a variable impedance load (first variable impedance load)
1
connected between the output terminal OUT and a ground terminal, a variable impedance load (second variable impedance load)
2
connected between the output terminal OUTn and the ground terminal, and a current generator
3
for supplying a bias voltage to a gate terminal of the PMOS transistor Q
1
.
The current generator bias circuit
3
includes a PMOS transistor Q
4
for functioning as a diode, and a NMOS transistor Q
5
. A BIAS signal applied to a gate terminal of the NMOS Q
5
can control the current passing through a source and a drain of the PMOS transistor Q
4
. The impedances of the variable impedance load
1
and
2
are controlled by a CONT signal.
Practically, the VCO has a plurality of VCO cells
10
connected in series, and the output of the VCO cell
10
at last stage is fed back to an input terminal of the VCO cell
10
at first stage, as shown in FIG.
2
.
In the circuit of
FIG. 1
, when the power supply voltage VDD is, for example, 1.5V, the current generator bias circuit
3
supplies bias so that the gate terminal of the PMOS transistor Q
1
becomes about 0.5V.
The VCO cell
10
controls the oscillating frequency by controlling impedances of the variable impedance loads
1
and
2
. The impedance values of the variable impedance loads
1
and
2
are controlled by a voltage of a CONT terminal. More specifically, when the voltage of the CONT terminal is high, the impedances of the variable impedance loads
1
and
2
go down and the oscillating frequency goes up. Conversely, when the voltage of the CONT terminal is low, impedances of the variable impedance loads
1
and
2
go up and the oscillating frequency goes down.
FIG. 3
is a diagram of plotting a relationship between the oscillating frequency of the VCO and the drain voltage of the PMOS transistor Q
1
composing of the current generator (the voltage of the node N
1
). The plots “X” of
FIG. 3
denote voltage change of the node N
1
in the circuit of FIG.
1
.
FIG. 3
shows a simulation result in the circuit using a CMOS technique of 0.35 &mgr;m.
As mentioned above, in case of lowering the oscillating frequency, the conventional VCO has performed control so that the impedances of the variable impedance loads
1
and
2
goes up. Because of this, as shown in
FIG. 1
, the lower the oscillating frequency is, the higher the voltage of the node N
1
becomes. For example, when the oscillating frequency is 200 MHz, the node N
1
reaches 1.35V.
In CMOS process of 0.35 &mgr;m, a threshold voltage of the PMOS transistor is 0.55V. Because of this, when the oscillating frequency of the VCO goes down, the PMOS transistor Q
1
deviates a pentode region (saturation region) and operates at a triode region (non-saturation region). In the triode region, the drain current ID changes largely in accordance with change of the voltage between the drain and the source. Because of this, there is a problem that constant current performance of the PMOS transistor Q
1
deteriorates in low frequency range.
In
FIG. 3
, the voltage level of the node N
1
in case of operating at 300 MHz is set to about 1.0V. However, when the voltage of the node N
1
is further lowered in order to avoid the triode operation of the PMOS transistor Q
1
, the output amplitude of the VCO becomes small, and a stable oscillation becomes difficult.
FIG. 4
is a diagram of plotting a relationship between the oscillating frequency of the VCO and a Cycle-to-Cycle jitter (hereinafter, called CC jitter). The plots “X” of
FIG. 4
denote a frequency change of the CC jitter in the circuit of FIG.
1
. Here, the CC jitter expresses fluctuation at each period of a difference &Dgr;Tj between each period T of the oscillating signal and an average period T
0
of the oscillating signal as shown in FIG.
5
.
FIG. 4
is a diagram of showing the result of calculating a square root average of the CC jitter in case of forcibly adding a sign wave noise by a simulation. As shown in
FIG. 4
, the lower the oscillating frequency of the VCO is, the more the CC jitter increases.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor integrated circuit and a phase locked loop circuit capable of performing stable oscillating operation and generating an oscillating signal with little jitter.
In order to achieve the foregoing object, a semiconductor integrated circuit, comprising:
a first FET connected between a first voltage terminal and a first node;
a second FET connected between said first node and a first output terminal;
a third FET connected between said first node and a second output terminal;
a first variable impedance load connected between said first output terminal and a second voltage terminal;
a second variable impedance load connected between said second output terminal and said second voltage terminal;
a first bias circuit connected between said first node and said second voltage terminal, said first bias circuit setting said first node to substantially a constant voltage, regardless of impedance values of said first and second variable impedance loads; and
a current generator bias circuit configured to supply a bias voltage to a gate terminal of said first FET,
wherein a first input terminal is connected to a gate terminal of said second FET, and a second input terminal is connected to a gate terminal of said third FET.
According to the present invention, a first bias circuit is provided between a first node and a second voltage terminal in order to perform control so that the first node is set to substantially a constant voltage. Because of this, even if impedances of the first and second variable impedance loads change, it is possible to allow the first MOSFFET to constantly operate at the pentode region. Accordingly, when composing of the voltage control oscillator by using the semiconductor integrated circuit according to the present invention, it is possible to allow the oscillating operation to stabilize, thereby reducing a Cycle-to-Cycle jitter of the oscillating signal.
Furthermore, a semiconductor integrated circuit, comprising:
a VCO cell circuit including a first FET connected between a first voltage terminal and a first node, a second FET connected between said first node and a first output terminal, a third FET connected between said first node and a second output terminal, a first variable impedance load connected between said first output terminal and a second voltage terminal, a second variable impedance load connected between said second outp

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