Static information storage and retrieval – Floating gate – Data security
Reexamination Certificate
2006-05-09
2008-09-23
Phan, Trong (Department: 2827)
Static information storage and retrieval
Floating gate
Data security
C365S185050, C365S185080, C365S185260, C365S185330
Reexamination Certificate
active
07428167
ABSTRACT:
A semiconductor integrated circuit device is provided on a semiconductor substrate, and includes a plurality of word lines, a plurality of data lines, and a plurality of electrically programmable and erasable non-volatile memory cells respectively coupled to the plurality of word lines and to the plurality of data lines. The erasable non-volatile memory cell each includes a MIS transistor having a floating gate having a first level polycrystalline silicon layer, a source, and a drain coupled to the corresponding data line, and a control gate formed of a semiconductor region in the semiconductor substrate, the control gate being coupled to the corresponding word line.
REFERENCES:
patent: 4040015 (1977-08-01), Fukuda
patent: 4279069 (1981-07-01), Beguwala et al.
patent: 4393474 (1983-07-01), McElroy et al.
patent: 5237530 (1993-08-01), Takashina et al.
patent: 5339279 (1994-08-01), Toms et al.
patent: 5465231 (1995-11-01), Ohsaki
patent: 5497475 (1996-03-01), Alapat
patent: 5694357 (1997-12-01), Mori
patent: 5719427 (1998-02-01), Tong et al.
patent: 5761126 (1998-06-01), Chi et al.
patent: 5828599 (1998-10-01), Herdt
patent: 5872994 (1999-02-01), Akiyama et al.
patent: 5937424 (1999-08-01), Leak et al.
patent: 5995409 (1999-11-01), Holland
patent: 5999446 (1999-12-01), Harari et al.
patent: 6026016 (2000-02-01), Gafken
patent: 6131139 (2000-10-01), Kikuchi et al.
patent: 6141256 (2000-10-01), Forbes
patent: 6181603 (2001-01-01), Jyouno et al.
patent: 6198663 (2001-03-01), Takizawa
patent: 6201733 (2001-03-01), Hiraki et al.
patent: 6229737 (2001-05-01), Walukas
patent: 0448118 (1991-09-01), None
patent: A-0470371 (1992-02-01), None
patent: 0828252 (1998-03-01), None
patent: A-0881571 (1998-12-01), None
patent: 263999 (1989-10-01), None
patent: 74392 (1992-03-01), None
patent: 127478 (1992-04-01), None
patent: 129091 (1992-04-01), None
patent: 163797 (1992-06-01), None
patent: 268180 (1994-09-01), None
patent: WO 94/18676 (1994-08-01), None
patent: WO98/19343 (1998-05-01), None
Ohsaki et al., “A Single Ploy EEPROM Cell Structure for Use in Standard CMOS Processes”, IEEE Journal of Solid-State Circuits, vol. 29, No. 3, Mar. 1994.
1988 IEEE International Solid-State Circuits Conference Thursday, Feb. 18, 1988/ A30ns Fault Tolerant 16k CMOS EEPROM pp. 128-129.
Ohsaki, K. et al: “SIPPOS (Single Poly Pure CMOS) EEPROM Embedded FPGA by News Ring Interconnection and Highway Path,” Advanced System Development, Component Technology, IBM Japan. IEEE 1994 Custom Integrated Circuits Conference, (pp. 189-192).
Komori Kazuhiro
Kubota Katsuhiko
Okuyama Kousuke
Shukuri Shoji
Antonelli, Terry Stout & Kraus, LLP.
Phan Trong
Renesas Technology Corp.
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