Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2000-08-31
2001-10-23
Nelms, David (Department: 2818)
Static information storage and retrieval
Addressing
Sync/clocking
C365S230030
Reexamination Certificate
active
06307806
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to technology for heightening the operating speed of a semiconductor integrated circuit.
2. Description of the Related Art
Semiconductor integrated circuits have steadily heightened their operating speed owing to the progress of semiconductor manufacturing technology. In particular, the operating frequency of a logic LSI such as microcomputer has been yearly enhanced, and the difference thereof from the operating frequency of a memory LSI such as DRAM has been expanding.
In order to reduce such difference, there have been developed high-speed DRAMs of clock synchronous type such as SDRAM (Synchronous DRAM), RDRAM (Rambus DRAM) and SLDRAM (SyncLink DRAM).
The high-speed DRAM of this type is possible to read and write the data of sequential addresses at high speed by an input/output circuit operating in synchronization with a clock signal, and an extended internal bus. Therefore, the high-speed DRAMs are often employed for the main storages of personal computers and workstations.
Meanwhile, in the high-speed DRAM of this type, the operating speed of a memory core is almost the same as that of a conventional DRAM. Consequently, the data transfer of (random access to) not sequential addresses is not much faster as compared with the data transfer of the sequential addresses.
As a result, it is sometimes difficult to adopt the high-speed DRAM due to a low data transfer rate in a field such as image processing, where the random access occurs frequently.
However, a DRAM capable of random access at high speed has been demanded even in such field since the DRAM is less expensive than an SRAM.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor integrated circuit capable of shortening the time required for the operation of its internal circuit.
Another object of the present invention is to provide a semiconductor integrated circuit capable of shortening the time required for the operation of its internal circuit without increasing the power consumption.
Still another object of the present invention is to perform random access at high speed in a semiconductor integrated circuit having memory cells.
Yet another object of the present invention is to further heighten the speed of burst access in a semiconductor integrated circuit having memory cells.
A further object of the present invention is to operate at high speed a redundancy circuit which relieves defects in a memory core.
According to one of the aspects of a semiconductor integrated circuit in the present invention, a command receiving circuit receives a command signal which indicates an operation mode of an internal circuit, in synchronization with a clock signal and it outputs an internal command signal. An address switching circuit permits transmission of an address signal to an internal circuit upon receiving the command signal. The internal circuit (for example, address decoder) receives the address signal before receiving the command signal, thereby to start its operation. As a result, the internal circuit can be operated at high speed.
Besides, the address switching circuit inhibits the transmission of the address signal to the internal circuit upon receiving the internal command signal or the clock signal. Therefore, even when the level of the address signal has changed after the acceptance of the command signal, the change does not lead to operating the internal circuit. Accordingly, the power consumption is reduced.
According to another aspect of the semiconductor integrated circuit in the present invention, this circuit comprises a memory core which includes a plurality of memory cells and a word line connected to the memory cells and it has the function of a burst operation in which the memory cells connected to the same word line are continuously accessed. A burst address counter generates a burst address signal for performing the burst operation. A burst switching circuit permits the transmission of the burst address signal to the internal circuit upon receiving a command signal for performing the burst operation. The internal circuit receives the burst address signal before receiving the command signal, thereby to start its operation. Accordingly, the internal circuit can be operated at high speed even in the semiconductor integrated circuit which has the function of the burst operation.
Besides, the burst switching circuit inhibits the transmission of the burst address signal to the internal circuit upon receiving the internal command signal for performing the burst operation, or the clock signal. Therefore, even when the level of a burst address has changed due to noise or the like after the receipt of the command signal, the internal circuit does not malfunction.
According to another aspect of the semiconductor integrated circuit in the present invention, this circuit comprises a redundancy circuit for relieving defects in the memory core, and a redundancy comparator for comparing the address signal and a defect address. The redundancy comparator can make the comparison between the address signal and the defect address before receiving the command signal. Therefore, in a case where the received address signal corresponds to a defect part, the redundancy circuit is possible to start its operation before the validation of the command. The time required for the operation of the internal circuit can be shortened.
According to another aspect of the semiconductor integrated circuit in the present invention, the address signal necessary for the read operation or the write operation of the memory core is fed to the internal circuit before the validation of the command. Therefore, the read operation or the write operation is performed at high speed.
According to another aspect of the semiconductor integrated circuit in the present invention, the address signal is transmitted to the internal circuit before accepting the command signal for activating a word line. For instance, the decoding of the row address signal for activating the word line is started earlier. That is, a circuit corresponding to the row address signal is operated earlier, whereby a subsequent read operation or write operation is performed at high speed.
According to another aspect of the semiconductor integrated circuit in the present invention, a period during which the address switching circuit inhibits the transmission of the address signal is variable. The address signal fed anew during the inhibitory period is not transmitted to the internal circuit. Therefore, the unnecessary operations of the internal circuit are minimized and the power consumption is reduced.
According to another aspect of the semiconductor integrated circuit in the present invention, the inhibitory period is modified in accordance with, for example, the frequency of the clock signal, whereby the internal circuit is operated at the optimum timing suited for each frequency.
According to another aspect of the semiconductor integrated circuit in the present invention, the period during which the transmission of the address signal is inhibited, is set in accordance with the frequency of the clock signal supplied or the factor of the operation environment such as temperature, at the start of or during the circuit operation.
According to another aspect of the semiconductor integrated circuit in the present invention, the period during which the transmission of the address signal is inhibited, is optimally set in accordance with, for example, the frequency of the clock signal supplied, at the time of operating the circuit or mounting the semiconductor integrated circuit on its printed-wiring board.
According to another of the aspects of the semiconductor integrated circuit in the present invention, the period during which the transmission of the address signal is inhibited, is set by blowing out fuses in accordance with, for example, the maximum operating frequency evaluated with a probing test. In other words, the inhibitory period is set in accordance with the charac
Shinozaki Naoharu
Tomita Hiroyoshi
Arent Fox Kintner & Plotkin & Kahn, PLLC
Fujitsu Limited
Nelms David
Tran M.
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