Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Field effect device in non-single crystal – or...
Reexamination Certificate
1999-04-14
2003-05-06
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Field effect device in non-single crystal, or...
C257S900000, C257S350000, C257S408000
Reexamination Certificate
active
06559478
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an integrated circuit comprising an insulating substrate on which insulated-gate semiconductor devices (TFTs) in the form of thin films are formed and also to a method of fabricating the integrated circuit. The insulated substrate referred to herein means a whole object having a dielectric surface and embraces semiconductors, metals, and other materials on which an insulator layer is formed, unless stated otherwise. Semiconductor integrated circuits according to the invention can be used in various circuits and devices, such as active matrix circuits of liquid crystal displays, their peripheral driver circuits, driver circuits for driving image sensors or the like, SOI integrated circuits, and conventional semiconductor integrated circuits (e.g., microprocessors, microcontrollers, microcomputers, and semiconductor memories, and so forth).
2. Description of the Related Art
Where an active matrix liquid crystal display, an image sensor circuit, or other circuit is formed on a glass substrate, use of integrated thin-film transistors (TFTs) has enjoyed wide acceptance. In this case, it is customary to first form a first wiring including a gate electrode. Then, an interlayer insulator layer is formed. Subsequently, a second wiring is formed. If necessary, a third and even a fourth wirings may be formed.
A serious problem with such a TFT integrated circuit is that the second wiring breaks at the intersections of this second wiring and a gate wiring which is an extension of a gate electrode. This is caused by the fact that it is difficult to form an interlayer insulator layer over a gate electrode and wiring with a good step coverage and to flatten the insulator layer.
FIG. 4
illustrates wiring breakage often occurring in the prior art TFT integrated circuit. A TFT region
401
and a gate wiring
402
are formed over a substrate. An interlayer insulator
403
is formed on these region and wiring. If the edges of the gate wiring
402
are sharp, the interlayer insulator
403
cannot fully cover the gate wiring. Under this condition, if the second wiring,
404
and
405
, is formed, it is likely that the second layer breaks, as shown, at portions
406
.
In order to prevent such wiring breakage, it is necessary to increase the thickness of the second wiring. For example, it has been desired to increase the thickness of the gate wiring about twofold. However, this means that the unevenness on the integrated circuit is increased further. If a further wiring is required to be deposited, breakage due to the thickness of the second wiring must be taken into consideration. Where an integrated circuit whose unevenness should be suppressed as in a liquid crystal display, it is substantially impossible to address the problem by increasing the thickness of the second wiring.
In an integrated circuit, if a wiring breakage occurs even at one edge of a step, then the whole circuit is made useless. Therefore, it is important to reduce wiring breakages at steps.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method of fabricating a semiconductor integrated circuit with minimum wiring breakages at steps and thus with improved production yield.
It is another object of the invention to provide a semiconductor integrated circuit in which wiring breakages at steps are reduced to a minimum.
In the present invention, after forming gate electrodes and gate wiring, a silicon nitride film is formed at least on their top surfaces, preferably even on their side surfaces, by plasma CVD or sputtering. Then, a substantially triangular regions (side walls) is formed out of the insulator on the side surfaces of the gate electrodes and of the gate wiring by anisotropic etching. Subsequently, an interlayer insulator is deposited, followed by formation of a second wiring. Silicon nitride exhibits a small etch rate under conditions in which silicon oxide forming the side walls is etched by dry etching. Therefore, the silicon nitride can be used as an etching stopper.
In a first method embodying the present invention, a semiconductor layer in the form of islands is first formed. A coating becoming a gate-insulating film is formed on the semiconductor layer. Then, gate electrodes and gate wiring are formed. Thereafter, silicon nitride is deposited as a film to a thickness of 100 to 2000 Å, preferably 200 to 1000 Å, by plasma-assisted CVD. Other CVD processes or sputtering techniques can also be employed. Thus, the first step of the inventive method is completed.
Then, a coating of an insulator is formed on the silicon nitride. In this stage of formation of the coating, the coverage is important. Preferably, the thickness of the coating is one-third to 2 times the height of the gate electrodes and the gate wiring. For this purpose, plasma-assisted CVD, LPCVD, atmospheric pressure CVD, and other CVD processes are preferably used. The insulator layer formed in this way is preferentially etched in a direction substantially vertical to the substrate by anisotropic etching. The etching terminates at the surface of the silicon nitride. The underlying gate electrodes and gate wiring are prevented from being etched.
As a result, substantially triangular regions of an insulator, or side walls, are left on the side surfaces of the gate electrodes and gate wiring, because the coating of the insulator is intrinsically thick on steps such as on the side surfaces of the gate electrodes and gate wiring. Thus, the second step of the inventive method is completed.
Then, an interlayer insulator is deposited. Contact holes are formed in one or both of source and drain regions of each TFT. The second wiring is formed, thus completing the third step of the inventive method.
Immediately after the side walls are formed in the second step, the film of silicon nitride can be etched by dry etching. Preferably, this etching step is performed while monitoring it with an endpoint monitor or other instrument. The etching of the film of silicon nitride can be controlled well with the monitor. The thickness of the etched silicon nitride film is 100 to 2000 Å. Therefore, even if overetching occurs, the depth is much smaller than the thickness of the gate electrodes and gate-insulating film. Hence, the gate electrodes and gate-insulating film are little affected thereby.
This method is effective where the gate-insulating film and the interlayer insulator are made from the same material different from silicon nitride. That is, if the interlayer insulator layer is formed after etching the silicon nitride film, the etching can be completed in one operation when the contact holes are formed.
Dopants are implanted to form the source and drain regions of each TFT. This implantation step can be varied variously. For example, where only N-channel TFTs are formed on a substrate, an N-type impurity may be introduced into the semiconductor layer at a relatively high concentration by self-alignment techniques, using the gate electrodes as a mask. This step is carried out between the first and second steps described above.
Similarly, where N-channel TFTs are formed, if they have the lightly doped drain (LDD) structure, an impurity is introduced into the semiconductor layer at a relatively low concentration. This step is effected between the first and second steps described above. Then, an N-type impurity is introduced into the semiconductor layer at a higher concentration by self-alignment techniques, using the gate electrodes and the side walls as a mask. This step is performed between the second and third steps described above. In this case, the width of the lightly doped drains is approximate to the width of the side walls.
Where only P-channel TFTs are formed on a substrate, similar steps may be carried out.
Where offset TFTs are fabricated, an impurity is introduced into the semiconductor layer at a high concentration, using the gate electrodes and side walls as a mask, by self-alignment techniques. This step is carried out betwe
Suzawa Hideomi
Takemura Yasuhiko
Prenty Mark V.
Robinson Eric J.
Robinson Intellectual Property Law Office P.C.
Semiconductor Energy Laboratory Co,. Ltd.
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