Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing
Reexamination Certificate
2008-05-21
2011-11-08
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Physical design processing
C716S111000, C716S112000
Reexamination Certificate
active
08056036
ABSTRACT:
A method of designing a semiconductor integrated circuit based on the TPI technique, comprising: (A) selecting a target node from a plurality of nodes included in a design circuit; (B) inserting a test point at the target node; (C) designating a delay time with respect to a test point path that is a path connected to the test point; and (D) laying out the design circuit such that a delay time of the test point path becomes the designated delay time. The (A) selecting includes: (A1) calculating delay times of fan-in paths and fan-out paths with respect to each of the plurality of nodes; and (A2) selecting the target node from the plurality of nodes based on the calculated delay times.
REFERENCES:
patent: 5819072 (1998-10-01), Bushard et al.
patent: 6038691 (2000-03-01), Nakao et al.
patent: 6247154 (2001-06-01), Bushnell et al.
patent: 6256759 (2001-07-01), Bhawmik et al.
patent: 6636995 (2003-10-01), Dean et al.
patent: 7051302 (2006-05-01), Xiang et al.
patent: 2001/0021990 (2001-09-01), Takeoka et al.
patent: 2002/0029361 (2002-03-01), Kasahara
patent: 2007/0288822 (2007-12-01), Lin et al.
patent: 6-331709 (1994-12-01), None
patent: 9-189748 (1997-07-01), None
patent: 2006-84427 (2006-03-01), None
S. Kajihara et al., “Aframework of High-quality Translation Fault ATPG for Scan Circuits”, IEEE International Test Conference, Paper 2.1, Oct. 2006.
Y. Sato et al., “Invisible Delay Quality—SDQM Model Lights Up What Could Not Be Seen”, IEEE International Test Conference, p. 47.1, Nov. 2005.
Asaka Toshiharu
Maeda Toshiyuki
Chiang Jack
McGinn IP Law Group PLLC
Renesas Electronics Corporation
Sandoval Patrick
LandOfFree
Semiconductor integrated circuit and method of designing... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor integrated circuit and method of designing..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit and method of designing... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4274220